MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices

[linux.git] / arch / mips / include / asm / mach-ralink / mt7621.h

diff --git a/arch/mips/include/asm/mach-ralink/mt7621.h b/arch/mips/include/asm/mach-ralink/mt7621.h
index a672e06fa5fd065ba492f6da7f45379b28b1e4b5..b8a8834164c861019ed89c79471e9ef6e17d634e 100644 (file)
--- a/arch/mips/include/asm/mach-ralink/mt7621.h
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -19,6 +19,10 @@
 #define SYSC_REG_CHIP_REV              0x0c
 #define SYSC_REG_SYSTEM_CONFIG0                0x10
 #define SYSC_REG_SYSTEM_CONFIG1                0x14
+#define SYSC_REG_CLKCFG0               0x2c
+#define SYSC_REG_CUR_CLK_STS           0x44
+
+#define MEMC_REG_CPU_PLL               0x648
 
 #define CHIP_REV_PKG_MASK              0x1
 #define CHIP_REV_PKG_SHIFT             16
@@ -26,6 +30,22 @@
 #define CHIP_REV_VER_SHIFT             8
 #define CHIP_REV_ECO_MASK              0xf
 
+#define XTAL_MODE_SEL_MASK             0x7
+#define XTAL_MODE_SEL_SHIFT            6
+
+#define CPU_CLK_SEL_MASK               0x3
+#define CPU_CLK_SEL_SHIFT              30
+
+#define CUR_CPU_FDIV_MASK              0x1f
+#define CUR_CPU_FDIV_SHIFT             8
+#define CUR_CPU_FFRAC_MASK             0x1f
+#define CUR_CPU_FFRAC_SHIFT            0
+
+#define CPU_PLL_PREDIV_MASK            0x3
+#define CPU_PLL_PREDIV_SHIFT           12
+#define CPU_PLL_FBDIV_MASK             0x7f
+#define CPU_PLL_FBDIV_SHIFT            4
+
 #define MT7621_DRAM_BASE                0x0
 #define MT7621_DDR2_SIZE_MIN           32
 #define MT7621_DDR2_SIZE_MAX           256