MIPS: c-r4k: Fix size calc when avoiding IPIs for small icache flushes

[linux.git] / arch / mips / mm / c-r4k.c

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 8016babe5c842161330324dad74c4653ba879ab4..fa7d8d3790bfc960bc7d4b358e9fb1a5120c04e2 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -68,7 +68,7 @@
 static inline bool r4k_op_needs_ipi(unsigned int type)
 {
        /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */
-       if (mips_cm_present())
+       if (type == R4K_HIT && mips_cm_present())
                return false;
 
        /*
@@ -800,7 +800,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end)
                 * If address-based cache ops don't require an SMP call, then
                 * use them exclusively for small flushes.
                 */
-               size = start - end;
+               size = end - start;
                cache_size = icache_size;
                if (!cpu_has_ic_fills_f_dc) {
                        size *= 2;
@@ -1376,7 +1376,7 @@ static void probe_pcache(void)
                              c->icache.linesz;
                c->icache.waybit = __ffs(icache_size/c->icache.ways);
 
-               if (config & 0x8)               /* VI bit */
+               if (config & MIPS_CONF_VI)
                        c->icache.flags |= MIPS_CACHE_VTAG;
 
                /*