clk: stm32mp1: Add ddrperfm clock

[linux.git] / drivers / clk / clk-stm32mp1.c

diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index 6a31f7f434ce47739bdeb548aa6154a013dfe1ae..a875649df8b8f1d6e02d2edfa20e6f4ee2d36768 100644 (file)
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -121,7 +121,7 @@ static const char * const cpu_src[] = {
 };
 
 static const char * const axi_src[] = {
-       "ck_hsi", "ck_hse", "pll2_p", "pll3_p"
+       "ck_hsi", "ck_hse", "pll2_p"
 };
 
 static const char * const per_src[] = {
@@ -225,19 +225,19 @@ static const char * const usart6_src[] = {
 };
 
 static const char * const fdcan_src[] = {
-       "ck_hse", "pll3_q", "pll4_q"
+       "ck_hse", "pll3_q", "pll4_q", "pll4_r"
 };
 
 static const char * const sai_src[] = {
-       "pll4_q", "pll3_q", "i2s_ckin", "ck_per"
+       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r"
 };
 
 static const char * const sai2_src[] = {
-       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb"
+       "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r"
 };
 
 static const char * const adc12_src[] = {
-       "pll4_q", "ck_per"
+       "pll4_r", "ck_per", "pll3_q"
 };
 
 static const char * const dsi_src[] = {
@@ -269,7 +269,7 @@ static const struct clk_div_table axi_div_table[] = {
 static const struct clk_div_table mcu_div_table[] = {
        { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
        { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 },
-       { 8, 512 }, { 9, 512 }, { 10, 512}, { 11, 512 },
+       { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 },
        { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 },
        { 0 },
 };
@@ -1286,10 +1286,11 @@ _clk_stm32_register_composite(struct device *dev,
        MGATE_MP1(_id, _name, _parent, _flags, _mgate)
 
 #define KCLK(_id, _name, _parents, _flags, _mgate, _mmux)\
-            COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE | _flags,\
-                 _MGATE_MP1(_mgate),\
-                 _MMUX(_mmux),\
-                 _NO_DIV)
+            COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
+                      CLK_SET_RATE_NO_REPARENT | _flags,\
+                      _MGATE_MP1(_mgate),\
+                      _MMUX(_mmux),\
+                      _NO_DIV)
 
 enum {
        G_SAI1,
@@ -1401,6 +1402,7 @@ enum {
        G_CRYP1,
        G_HASH1,
        G_BKPSRAM,
+       G_DDRPERFM,
 
        G_LAST
 };
@@ -1487,6 +1489,7 @@ static struct stm32_gate_cfg per_gate_cfg[G_LAST] = {
        K_GATE(G_STGENRO,       RCC_APB4ENSETR, 20, 0),
        K_MGATE(G_USBPHY,       RCC_APB4ENSETR, 16, 0),
        K_GATE(G_IWDG2,         RCC_APB4ENSETR, 15, 0),
+       K_GATE(G_DDRPERFM,      RCC_APB4ENSETR, 8, 0),
        K_MGATE(G_DSI,          RCC_APB4ENSETR, 4, 0),
        K_MGATE(G_LTDC,         RCC_APB4ENSETR, 0, 0),
 
@@ -1655,12 +1658,14 @@ static const struct stm32_mux_cfg ker_mux_cfg[M_LAST] = {
 
 static const struct clock_config stm32mp1_clock_cfg[] = {
        /* Oscillator divider */
-       DIV(NO_ID, "clk-hsi-div", "clk-hsi", 0, RCC_HSICFGR, 0, 2,
-           CLK_DIVIDER_READ_ONLY),
+       DIV(NO_ID, "clk-hsi-div", "clk-hsi", CLK_DIVIDER_POWER_OF_TWO,
+           RCC_HSICFGR, 0, 2, CLK_DIVIDER_READ_ONLY),
 
        /*  External / Internal Oscillators */
        GATE_MP1(CK_HSE, "ck_hse", "clk-hse", 0, RCC_OCENSETR, 8, 0),
-       GATE_MP1(CK_CSI, "ck_csi", "clk-csi", 0, RCC_OCENSETR, 4, 0),
+       /* ck_csi is used by IO compensation and should be critical */
+       GATE_MP1(CK_CSI, "ck_csi", "clk-csi", CLK_IS_CRITICAL,
+                RCC_OCENSETR, 4, 0),
        GATE_MP1(CK_HSI, "ck_hsi", "clk-hsi-div", 0, RCC_OCENSETR, 0, 0),
        GATE(CK_LSI, "ck_lsi", "clk-lsi", 0, RCC_RDLSICR, 0, 0),
        GATE(CK_LSE, "ck_lse", "clk-lse", 0, RCC_BDCR, 0, 0),
@@ -1896,6 +1901,7 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        PCLK(CRC1, "crc1", "ck_axi", 0, G_CRC1),
        PCLK(USBH, "usbh", "ck_axi", 0, G_USBH),
        PCLK(ETHSTP, "ethstp", "ck_axi", 0, G_ETHSTP),
+       PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, G_DDRPERFM),
 
        /* Kernel clocks */
        KCLK(SDMMC1_K, "sdmmc1_k", sdmmc12_src, 0, G_SDMMC1, M_SDMMC12),
@@ -1952,14 +1958,14 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
        MGATE_MP1(GPU_K, "gpu_k", "pll2_q", 0, G_GPU),
        MGATE_MP1(DAC12_K, "dac12_k", "ck_lsi", 0, G_DAC12),
 
-       COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE,
+       COMPOSITE(ETHPTP_K, "ethptp_k", eth_src, CLK_OPS_PARENT_ENABLE |
+                 CLK_SET_RATE_NO_REPARENT,
                  _NO_GATE,
                  _MMUX(M_ETHCK),
-                 _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)),
+                 _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)),
 
        /* RTC clock */
-       DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7,
-           CLK_DIVIDER_ALLOW_ZERO),
+       DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 6, 0),
 
        COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE |
                   CLK_SET_RATE_PARENT,