]> asedeno.scripts.mit.edu Git - linux.git/blobdiff - drivers/clk/qcom/clk-rcg2.c
Merge branch 'hinic-BugFixes'
[linux.git] / drivers / clk / qcom / clk-rcg2.c
index da045b200deff4d21293c8079d9a320b1160e66c..357159fe85b5e7d07308fa5a10f4ba61a088264f 100644 (file)
@@ -218,6 +218,9 @@ static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
 
        clk_flags = clk_hw_get_flags(hw);
        p = clk_hw_get_parent_by_index(hw, index);
+       if (!p)
+               return -EINVAL;
+
        if (clk_flags & CLK_SET_RATE_PARENT) {
                rate = f->freq;
                if (f->pre_div) {
@@ -953,7 +956,7 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
        struct clk_rcg2 *rcg = to_clk_rcg2(hw);
        struct clk_hw *p;
        unsigned long prate = 0;
-       u32 val, mask, cfg, mode;
+       u32 val, mask, cfg, mode, src;
        int i, num_parents;
 
        regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
@@ -963,12 +966,12 @@ static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
        if (cfg & mask)
                f->pre_div = cfg & mask;
 
-       cfg &= CFG_SRC_SEL_MASK;
-       cfg >>= CFG_SRC_SEL_SHIFT;
+       src = cfg & CFG_SRC_SEL_MASK;
+       src >>= CFG_SRC_SEL_SHIFT;
 
        num_parents = clk_hw_get_num_parents(hw);
        for (i = 0; i < num_parents; i++) {
-               if (cfg == rcg->parent_map[i].cfg) {
+               if (src == rcg->parent_map[i].cfg) {
                        f->src = rcg->parent_map[i].src;
                        p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
                        prate = clk_hw_get_rate(p);