Merge branch 'clk-renesas' into clk-next

[linux.git] / drivers / clk / renesas / rcar-gen3-cpg.h

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 6ebc4b42c5a3b584cee41fe3e98312ba017fb028..f4fb6cf16688cfb3d34a07f8add2764a181c46d9 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -2,7 +2,8 @@
  *
  * R-Car Gen3 Clock Pulse Generator
  *
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
+ *
  */
 
 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
@@ -17,19 +18,35 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_PLL4,
        CLK_TYPE_GEN3_SD,
        CLK_TYPE_GEN3_R,
-       CLK_TYPE_GEN3_PE,
+       CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
        CLK_TYPE_GEN3_Z,
        CLK_TYPE_GEN3_Z2,
+       CLK_TYPE_GEN3_OSC,      /* OSC EXTAL predivider and fixed divider */
+       CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
+
+       /* SoC specific definitions start here */
+       CLK_TYPE_GEN3_SOC_BASE,
 };
 
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)      \
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 
+#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,       \
+                (_parent0) << 16 | (_parent1),         \
+                .div = (_div0) << 16 | (_div1), .offset = _md)
+
 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
                    _div_clean) \
-       DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE,                  \
-                (_parent_sscg) << 16 | (_parent_clean),        \
-                .div = (_div_sscg) << 16 | (_div_clean))
+       DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
+                      _parent_clean, _div_clean)
+
+#define DEF_GEN3_OSC(_name, _id, _parent, _div)                \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
+
+#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL,      \
+                (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
 
 struct rcar_gen3_cpg_pll_config {
        u8 extal_div;
@@ -37,6 +54,7 @@ struct rcar_gen3_cpg_pll_config {
        u8 pll1_div;
        u8 pll3_mult;
        u8 pll3_div;
+       u8 osc_prediv;
 };
 
 #define CPG_RCKCR      0x240