Merge tag 'v4.20-rc1' into patchwork

[linux.git] / drivers / clk / uniphier / clk-uniphier-sys.c

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 4f5ff9fa11fdde223bb3600a3359a48b62559df6..2bb5a8570adc96a6b19c1c165663d32c6930f6b1 100644 (file)
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -29,18 +29,20 @@
        UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10),              \
        UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
 
-/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
 #define UNIPHIER_LD4_SYS_CLK_NAND(idx)                                 \
-       UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8),             \
-       UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
+       UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32),             \
+       UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
 
 #define UNIPHIER_PRO5_SYS_CLK_NAND(idx)                                        \
-       UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 12),            \
-       UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
+       UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48),             \
+       UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
 
 #define UNIPHIER_LD11_SYS_CLK_NAND(idx)                                        \
-       UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 10),            \
-       UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x210c, 0)
+       UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40),             \
+       UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
+
+#define UNIPHIER_SYS_CLK_NAND_4X(idx)                                  \
+       UNIPHIER_CLK_FACTOR("nand-4x", (idx), "nand", 4, 1)
 
 #define UNIPHIER_LD11_SYS_CLK_EMMC(idx)                                        \
        UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
@@ -93,7 +95,9 @@ const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),   /* 270 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
        UNIPHIER_LD4_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD4_SYS_CLK_SD,
        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
@@ -108,7 +112,9 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),          /* 250 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
+       UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),
        UNIPHIER_LD4_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD4_SYS_CLK_SD,
        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
@@ -118,6 +124,9 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = {
        UNIPHIER_PRO4_SYS_CLK_GIO(12),                  /* Ether, SATA, USB3 */
        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+       UNIPHIER_CLK_FACTOR("usb30-hsphy0", 16, "upll", 1, 12),
+       UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
+       UNIPHIER_CLK_FACTOR("usb31-ssphy0", 20, "ref", 1, 1),
        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
        UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
        UNIPHIER_PRO4_SYS_CLK_AIO(40),
@@ -130,7 +139,9 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),     /* 270 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),
        UNIPHIER_LD4_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD4_SYS_CLK_SD,
        UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                 /* Ether, HSC, MIO */
@@ -143,7 +154,9 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),  /* 2949.12 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
        UNIPHIER_PRO5_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_PRO5_SYS_CLK_SD,
        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC */
        UNIPHIER_PRO4_SYS_CLK_GIO(12),                          /* PCIe, USB3 */
@@ -158,7 +171,9 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),          /* 2400 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),
        UNIPHIER_PRO5_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_PRO5_SYS_CLK_SD,
        UNIPHIER_PRO4_SYS_CLK_ETHER(6),
        UNIPHIER_LD4_SYS_CLK_STDMAC(8),                         /* HSC, RLE */
@@ -166,8 +181,11 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = {
        UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
        UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
        /* The document mentions 0x2104 bit 18, but not functional */
-       UNIPHIER_CLK_GATE("usb30-phy", 16, NULL, 0x2104, 19),
-       UNIPHIER_CLK_GATE("usb31-phy", 20, NULL, 0x2104, 20),
+       UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
+       UNIPHIER_CLK_FACTOR("usb30-ssphy0", 17, "ref", 1, 1),
+       UNIPHIER_CLK_FACTOR("usb30-ssphy1", 18, "ref", 1, 1),
+       UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
+       UNIPHIER_CLK_FACTOR("usb31-ssphy0", 21, "ref", 1, 1),
        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
        UNIPHIER_PRO5_SYS_CLK_AIO(40),
        { /* sentinel */ }
@@ -180,7 +198,9 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),         /* 2000 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
        UNIPHIER_LD11_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD11_SYS_CLK_EMMC(4),
        /* Index 5 reserved for eMMC PHY */
        UNIPHIER_LD11_SYS_CLK_ETHER(6),
@@ -213,7 +233,9 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),        /* 2520 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
        UNIPHIER_LD11_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD11_SYS_CLK_EMMC(4),
        /* Index 5 reserved for eMMC PHY */
        UNIPHIER_LD20_SYS_CLK_SD,
@@ -226,8 +248,10 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
         * We do not use bit 15 here.
         */
        UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
-       UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
-       UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+       UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
+       UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
+       UNIPHIER_CLK_FACTOR("usb30-ssphy0", 18, "ref", 1, 1),
+       UNIPHIER_CLK_FACTOR("usb30-ssphy1", 19, "ref", 1, 1),
        UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
        UNIPHIER_LD11_SYS_CLK_AIO(40),
        UNIPHIER_LD11_SYS_CLK_EVEA(41),
@@ -254,19 +278,21 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = {
        UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),         /* IPP: 2400 MHz */
        UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
        UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),
+       UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),
        UNIPHIER_LD20_SYS_CLK_SD,
        UNIPHIER_LD11_SYS_CLK_NAND(2),
+       UNIPHIER_SYS_CLK_NAND_4X(3),
        UNIPHIER_LD11_SYS_CLK_EMMC(4),
        UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
        UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
        UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4),        /* =GIO0 */
        UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5),      /* =GIO1 */
        UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6),      /* =GIO1-1 */
-       UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 16),
-       UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 18),
-       UNIPHIER_CLK_GATE("usb30-phy2", 18, NULL, 0x210c, 20),
-       UNIPHIER_CLK_GATE("usb31-phy0", 20, NULL, 0x210c, 17),
-       UNIPHIER_CLK_GATE("usb31-phy1", 21, NULL, 0x210c, 19),
+       UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
+       UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
+       UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
+       UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
+       UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
        UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
        UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
        UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),