drm/amdgpu: clean up load TMR sequence

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_psp.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 8466f706a4e6eb3300042e0349a70c2aafb7c781..1978e9823bc6d78211f21313b106dbde3ce5f856 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -144,8 +144,7 @@ psp_cmd_submit_buf(struct psp_context *psp,
        memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 
        index = atomic_inc_return(&psp->fence_value);
-       ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
-                            fence_mc_addr, index);
+       ret = psp_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
        if (ret) {
                atomic_dec(&psp->fence_value);
                mutex_unlock(&psp->mutex);
@@ -240,6 +239,8 @@ static int psp_tmr_init(struct psp_context *psp)
 {
        int ret;
        int tmr_size;
+       void *tmr_buf;
+       void **pptr;
 
        /*
         * According to HW engineer, they prefer the TMR address be "naturally
@@ -262,9 +263,10 @@ static int psp_tmr_init(struct psp_context *psp)
                }
        }
 
+       pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
        ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
                                      AMDGPU_GEM_DOMAIN_VRAM,
-                                     &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+                                     &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 
        return ret;
 }
@@ -285,15 +287,9 @@ static int psp_tmr_load(struct psp_context *psp)
 
        ret = psp_cmd_submit_buf(psp, NULL, cmd,
                                 psp->fence_buf_mc_addr);
-       if (ret)
-               goto failed;
 
        kfree(cmd);
 
-       return 0;
-
-failed:
-       kfree(cmd);
        return ret;
 }
 
@@ -944,6 +940,60 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
        return 0;
 }
 
+static void psp_print_fw_hdr(struct psp_context *psp,
+                            struct amdgpu_firmware_info *ucode)
+{
+       struct amdgpu_device *adev = psp->adev;
+       const struct sdma_firmware_header_v1_0 *sdma_hdr =
+               (const struct sdma_firmware_header_v1_0 *)
+               adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
+       const struct gfx_firmware_header_v1_0 *ce_hdr =
+               (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
+       const struct gfx_firmware_header_v1_0 *pfp_hdr =
+               (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
+       const struct gfx_firmware_header_v1_0 *me_hdr =
+               (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
+       const struct gfx_firmware_header_v1_0 *mec_hdr =
+               (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
+       const struct rlc_firmware_header_v2_0 *rlc_hdr =
+               (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
+       const struct smc_firmware_header_v1_0 *smc_hdr =
+               (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
+
+       switch (ucode->ucode_id) {
+       case AMDGPU_UCODE_ID_SDMA0:
+       case AMDGPU_UCODE_ID_SDMA1:
+       case AMDGPU_UCODE_ID_SDMA2:
+       case AMDGPU_UCODE_ID_SDMA3:
+       case AMDGPU_UCODE_ID_SDMA4:
+       case AMDGPU_UCODE_ID_SDMA5:
+       case AMDGPU_UCODE_ID_SDMA6:
+       case AMDGPU_UCODE_ID_SDMA7:
+               amdgpu_ucode_print_sdma_hdr(&sdma_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_CP_CE:
+               amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_CP_PFP:
+               amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_CP_ME:
+               amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_CP_MEC1:
+               amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_RLC_G:
+               amdgpu_ucode_print_rlc_hdr(&rlc_hdr->header);
+               break;
+       case AMDGPU_UCODE_ID_SMC:
+               amdgpu_ucode_print_smc_hdr(&smc_hdr->header);
+               break;
+       default:
+               break;
+       }
+}
+
 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
                                       struct psp_gfx_cmd_resp *cmd)
 {
@@ -1028,13 +1078,14 @@ static int psp_np_fw_load(struct psp_context *psp)
                    ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT)
                        continue;
 
+               psp_print_fw_hdr(psp, ucode);
+
                ret = psp_execute_np_fw_load(psp, ucode);
                if (ret)
                        return ret;
 
                /* Start rlc autoload after psp recieved all the gfx firmware */
-               if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM ||
-                   (adev->asic_type == CHIP_NAVI12 && ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G)) {
+               if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) {
                        ret = psp_rlc_autoload(psp);
                        if (ret) {
                                DRM_ERROR("Failed to start rlc autoload\n");
@@ -1152,6 +1203,8 @@ static int psp_hw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct psp_context *psp = &adev->psp;
+       void *tmr_buf;
+       void **pptr;
 
        if (adev->gmc.xgmi.num_physical_nodes > 1 &&
            psp->xgmi_context.initialized == 1)
@@ -1162,7 +1215,8 @@ static int psp_hw_fini(void *handle)
 
        psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
-       amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
+       pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
+       amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
        amdgpu_bo_free_kernel(&psp->fw_pri_bo,
                              &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
        amdgpu_bo_free_kernel(&psp->fence_buf_bo,