drm/amdgpu: add graceful VM fault handling v3

[linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vm.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 489a162ca6207775b7bdcc3408bb0d77911701b9..4dbbe1b6b413604e33ae7be5abfffc36dcdd45f4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -90,7 +90,7 @@ struct amdgpu_bo_list_entry;
                                 | AMDGPU_PTE_WRITEABLE  \
                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
 
-/* NAVI10 only */
+/* gfx10 */
 #define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
 #define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
 
@@ -99,10 +99,14 @@ struct amdgpu_bo_list_entry;
 #define AMDGPU_VM_FAULT_STOP_FIRST     1
 #define AMDGPU_VM_FAULT_STOP_ALWAYS    2
 
+/* Reserve 4MB VRAM for page tables */
+#define AMDGPU_VM_RESERVED_VRAM                (4ULL << 20)
+
 /* max number of VMHUB */
-#define AMDGPU_MAX_VMHUBS                      2
-#define AMDGPU_GFXHUB                          0
-#define AMDGPU_MMHUB                           1
+#define AMDGPU_MAX_VMHUBS                      3
+#define AMDGPU_GFXHUB_0                                0
+#define AMDGPU_MMHUB_0                         1
+#define AMDGPU_MMHUB_1                         2
 
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE                        (1ULL << 20)
@@ -197,6 +201,11 @@ struct amdgpu_vm_update_params {
         */
        struct amdgpu_vm *vm;
 
+       /**
+        * @direct: if changes should be made directly
+        */
+       bool direct;
+
        /**
         * @pages_addr:
         *
@@ -253,8 +262,9 @@ struct amdgpu_vm {
        struct amdgpu_vm_pt     root;
        struct dma_fence        *last_update;
 
-       /* Scheduler entity for page table updates */
-       struct drm_sched_entity entity;
+       /* Scheduler entities for page table updates */
+       struct drm_sched_entity direct;
+       struct drm_sched_entity delayed;
 
        unsigned int            pasid;
        /* dedicated to vm */
@@ -356,8 +366,8 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
                              int (*callback)(void *p, struct amdgpu_bo *bo),
                              void *param);
 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
-int amdgpu_vm_update_directories(struct amdgpu_device *adev,
-                                struct amdgpu_vm *vm);
+int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
+                         struct amdgpu_vm *vm, bool direct);
 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
                          struct amdgpu_vm *vm,
                          struct dma_fence **fence);
@@ -403,6 +413,8 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
 
 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
                             struct amdgpu_task_info *task_info);
+bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
+                           uint64_t addr);
 
 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);