drm/amdgpu:fix NULL pointer access during drv remove

[linux.git] / drivers / gpu / drm / amd / amdgpu / gmc_v6_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index f4603a7c8ef32e193aa83f76d0380283ccc7cdc0..9c672ece9f185110b22bb67f3e950f8abbf5ca7a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -283,6 +283,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
 
        u32 tmp;
        int chansize, numchan;
+       int r;
 
        tmp = RREG32(mmMC_ARB_RAMCFG);
        if (tmp & (1 << 11)) {
@@ -324,12 +325,17 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
                break;
        }
        adev->mc.vram_width = numchan * chansize;
-       /* Could aper size report 0 ? */
-       adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
-       adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
        /* size in MB on si */
        adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
        adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
+
+       if (!(adev->flags & AMD_IS_APU)) {
+               r = amdgpu_device_resize_fb_bar(adev);
+               if (r)
+                       return r;
+       }
+       adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
+       adev->mc.aper_size = pci_resource_len(adev->pdev, 0);
        adev->mc.visible_vram_size = adev->mc.aper_size;
 
        /* set the gart size */
@@ -477,16 +483,14 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
-       int r, i;
+       int i;
        u32 field;
 
        if (adev->gart.robj == NULL) {
                dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
-       r = amdgpu_gart_table_vram_pin(adev);
-       if (r)
-               return r;
+
        /* Setup TLB control */
        WREG32(mmMC_VM_MX_L1_TLB_CNTL,
               (0xA << 7) |
@@ -613,7 +617,6 @@ static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
        WREG32(mmVM_L2_CNTL3,
               VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
               (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
-       amdgpu_gart_table_vram_unpin(adev);
 }
 
 static void gmc_v6_0_gart_fini(struct amdgpu_device *adev)
@@ -832,7 +835,6 @@ static int gmc_v6_0_sw_init(void *handle)
                return r;
 
        amdgpu_vm_adjust_size(adev, 64, 9);
-       adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
 
        adev->mc.mc_mask = 0xffffffffffULL;
 
@@ -897,9 +899,9 @@ static int gmc_v6_0_sw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       amdgpu_gem_force_release(adev);
        amdgpu_vm_manager_fini(adev);
        gmc_v6_0_gart_fini(adev);
-       amdgpu_gem_force_release(adev);
        amdgpu_bo_fini(adev);
        release_firmware(adev->mc.fw);
        adev->mc.fw = NULL;