Merge tag 'ras-urgent-2020-02-22' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux.git] / drivers / gpu / drm / amd / amdgpu / vcn_v1_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 1a24fadd30e2da76d1c2a9cd3760f50edfdeb1ef..71f61afdc6551d6c04f1d051ff7643fd51d6f2eb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1207,9 +1207,10 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
        struct amdgpu_ring *ring;
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
+       if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
                DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
-                       adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,
+                       adev->vcn.inst[inst_idx].pause_state.jpeg,
                        new_state->fw_based, new_state->jpeg);
 
                reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1258,13 +1259,14 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.fw_based = new_state->fw_based;
+               adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
        }
 
        /* pause/unpause if state is changed */
-       if (adev->vcn.pause_state.jpeg != new_state->jpeg) {
+       if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
                DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
-                       adev->vcn.pause_state.fw_based, adev->vcn.pause_state.jpeg,
+                       adev->vcn.inst[inst_idx].pause_state.fw_based,
+                       adev->vcn.inst[inst_idx].pause_state.jpeg,
                        new_state->fw_based, new_state->jpeg);
 
                reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
@@ -1318,7 +1320,7 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
                        reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
                        WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
                }
-               adev->vcn.pause_state.jpeg = new_state->jpeg;
+               adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
        }
 
        return 0;