]> asedeno.scripts.mit.edu Git - linux.git/blobdiff - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
drm/amd/dm/mst: Ignore payload update failures
[linux.git] / drivers / gpu / drm / amd / display / amdgpu_dm / amdgpu_dm_helpers.c
index 11e5784aa62a15cc2d66b0270c9d7dda99e2e2a8..318b474ff20ee33f5090c22643a5fd8d697588f0 100644 (file)
@@ -37,6 +37,7 @@
 #include "dc.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_irq.h"
+#include "amdgpu_dm_mst_types.h"
 
 #include "dm_helpers.h"
 
@@ -97,8 +98,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps(
                        (struct edid *) edid->raw_edid);
 
        sad_count = drm_edid_to_sad((struct edid *) edid->raw_edid, &sads);
-       if (sad_count < 0)
-               DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
        if (sad_count <= 0)
                return result;
 
@@ -182,19 +181,22 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
                bool enable)
 {
        struct amdgpu_dm_connector *aconnector;
+       struct dm_connector_state *dm_conn_state;
        struct drm_dp_mst_topology_mgr *mst_mgr;
        struct drm_dp_mst_port *mst_port;
-       int slots = 0;
        bool ret;
-       int clock;
-       int bpp = 0;
-       int pbn = 0;
 
        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+       /* Accessing the connector state is required for vcpi_slots allocation
+        * and directly relies on behaviour in commit check
+        * that blocks before commit guaranteeing that the state
+        * is not gonna be swapped while still in use in commit tail */
 
        if (!aconnector || !aconnector->mst_port)
                return false;
 
+       dm_conn_state = to_dm_connector_state(aconnector->base.state);
+
        mst_mgr = &aconnector->mst_port->mst_mgr;
 
        if (!mst_mgr->mst_state)
@@ -203,42 +205,10 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
        mst_port = aconnector->port;
 
        if (enable) {
-               clock = stream->timing.pix_clk_100hz / 10;
-
-               switch (stream->timing.display_color_depth) {
-
-               case COLOR_DEPTH_666:
-                       bpp = 6;
-                       break;
-               case COLOR_DEPTH_888:
-                       bpp = 8;
-                       break;
-               case COLOR_DEPTH_101010:
-                       bpp = 10;
-                       break;
-               case COLOR_DEPTH_121212:
-                       bpp = 12;
-                       break;
-               case COLOR_DEPTH_141414:
-                       bpp = 14;
-                       break;
-               case COLOR_DEPTH_161616:
-                       bpp = 16;
-                       break;
-               default:
-                       ASSERT(bpp != 0);
-                       break;
-               }
-
-               bpp = bpp * 3;
-
-               /* TODO need to know link rate */
-
-               pbn = drm_dp_calc_pbn_mode(clock, bpp);
-
-               slots = drm_dp_find_vcpi_slots(mst_mgr, pbn);
-               ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots);
 
+               ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port,
+                                              dm_conn_state->pbn,
+                                              dm_conn_state->vcpi_slots);
                if (!ret)
                        return false;
 
@@ -246,7 +216,8 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
                drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port);
        }
 
-       ret = drm_dp_update_payload_part1(mst_mgr);
+       /* It's OK for this to fail */
+       drm_dp_update_payload_part1(mst_mgr);
 
        /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or
         * AUX message. The sequence is slot 1-63 allocated sequence for each
@@ -255,9 +226,6 @@ bool dm_helpers_dp_mst_write_payload_allocation_table(
 
        get_payload_table(aconnector, proposed_table);
 
-       if (ret)
-               return false;
-
        return true;
 }
 
@@ -315,7 +283,6 @@ bool dm_helpers_dp_mst_send_payload_allocation(
        struct amdgpu_dm_connector *aconnector;
        struct drm_dp_mst_topology_mgr *mst_mgr;
        struct drm_dp_mst_port *mst_port;
-       int ret;
 
        aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
 
@@ -329,10 +296,8 @@ bool dm_helpers_dp_mst_send_payload_allocation(
        if (!mst_mgr->mst_state)
                return false;
 
-       ret = drm_dp_update_payload_part2(mst_mgr);
-
-       if (ret)
-               return false;
+       /* It's OK for this to fail */
+       drm_dp_update_payload_part2(mst_mgr);
 
        if (!enable)
                drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port);
@@ -540,7 +505,6 @@ bool dm_helpers_submit_i2c(
 
        return result;
 }
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
 bool dm_helpers_dp_write_dsc_enable(
                struct dc_context *ctx,
                const struct dc_stream_state *stream,
@@ -548,10 +512,25 @@ bool dm_helpers_dp_write_dsc_enable(
 )
 {
        uint8_t enable_dsc = enable ? 1 : 0;
+       struct amdgpu_dm_connector *aconnector;
+
+       if (!stream)
+               return false;
+
+       if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+               aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+
+               if (!aconnector->dsc_aux)
+                       return false;
+
+               return (drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1) >= 0);
+       }
+
+       if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT)
+               return dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1);
 
-       return dm_helpers_dp_write_dpcd(ctx, stream->sink->link, DP_DSC_ENABLE, &enable_dsc, 1);
+       return false;
 }
-#endif
 
 bool dm_helpers_is_dp_sink_present(struct dc_link *link)
 {