]> asedeno.scripts.mit.edu Git - linux.git/blobdiff - drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
drm/amd/display: define DC_LOGGER for logger
[linux.git] / drivers / gpu / drm / amd / display / dc / calcs / dcn_calcs.c
index 7728c85bcb0e32714e1f00769cb9e15f195c1350..f1d8db56f406f73c3f4209b21c722d7e00a83004 100644 (file)
@@ -33,6 +33,8 @@
 #include "dcn10/dcn10_resource.h"
 #include "dcn_calc_math.h"
 
+#define DC_LOGGER \
+       dc->ctx->logger
 /*
  * NOTE:
  *   This file is gcc-parseable HW gospel, coming straight from HW engineers.
@@ -1242,8 +1244,7 @@ unsigned int dcn_find_dcfclk_suits_all(
        else
                dcf_clk =  dc->dcn_soc->dcfclkv_min0p65*1000;
 
-       DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-               "\tdcf_clk for voltage = %d\n", dcf_clk);
+       DC_LOG_BANDWIDTH_CALCS("\tdcf_clk for voltage = %d\n", dcf_clk);
        return dcf_clk;
 }
 
@@ -1441,8 +1442,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
 {
        kernel_fpu_begin();
-       DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-                       "sr_exit_time: %d ns\n"
+       DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %d ns\n"
                        "sr_enter_plus_exit_time: %d ns\n"
                        "urgent_latency: %d ns\n"
                        "write_back_latency: %d ns\n"
@@ -1510,8 +1510,7 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
                        dc->dcn_soc->vmm_page_size,
                        dc->dcn_soc->dram_clock_change_latency * 1000,
                        dc->dcn_soc->return_bus_width);
-       DC_LOG_BANDWIDTH_CALCS(dc->ctx->logger,
-                       "rob_buffer_size_in_kbyte: %d\n"
+       DC_LOG_BANDWIDTH_CALCS("rob_buffer_size_in_kbyte: %d\n"
                        "det_buffer_size_in_kbyte: %d\n"
                        "dpp_output_buffer_pixels: %d\n"
                        "opp_output_buffer_lines: %d\n"