drm/amd/display: define DC_LOGGER for logger

[linux.git] / drivers / gpu / drm / amd / display / dc / dce / dce_clock_source.c

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 2860d0a39be45728549bcb811388a2a721326c49..0aa2cda6089093108935a87acda8185a1664b135 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -41,7 +41,8 @@
 
 #define CTX \
        clk_src->base.ctx
-
+#define DC_LOGGER \
+       calc_pll_cs->ctx->logger
 #undef FN
 #define FN(reg_name, field_name) \
        clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
@@ -288,7 +289,7 @@ static uint32_t calculate_pixel_clock_pll_dividers(
        uint32_t max_ref_divider;
 
        if (pll_settings->adjusted_pix_clk == 0) {
-               DC_LOG_ERROR(calc_pll_cs->ctx->logger,
+               DC_LOG_ERROR(
                        "%s Bad requested pixel clock", __func__);
                return MAX_PLL_CALC_ERROR;
        }
@@ -349,13 +350,13 @@ static uint32_t calculate_pixel_clock_pll_dividers(
  *  ## SVS Wed 15 Jul 2009 */
 
        if (min_post_divider > max_post_divider) {
-               DC_LOG_ERROR(calc_pll_cs->ctx->logger,
+               DC_LOG_ERROR(
                        "%s Post divider range is invalid", __func__);
                return MAX_PLL_CALC_ERROR;
        }
 
        if (min_ref_divider > max_ref_divider) {
-               DC_LOG_ERROR(calc_pll_cs->ctx->logger,
+               DC_LOG_ERROR(
                        "%s Reference divider range is invalid", __func__);
                return MAX_PLL_CALC_ERROR;
        }
@@ -466,7 +467,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
 {
        uint32_t field = 0;
        uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
-
+       struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
        /* Check if reference clock is external (not pcie/xtalin)
        * HW Dce80 spec:
        * 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
@@ -493,7 +494,7 @@ static uint32_t dce110_get_pix_clk_dividers_helper (
        if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
                /* Should never happen, ASSERT and fill up values to be able
                 * to continue. */
-               DC_LOG_ERROR(clk_src->base.ctx->logger,
+               DC_LOG_ERROR(
                        "%s: Failed to adjust pixel clock!!", __func__);
                pll_settings->actual_pix_clk =
                                pix_clk_params->requested_pix_clk;
@@ -556,11 +557,12 @@ static uint32_t dce110_get_pix_clk_dividers(
                struct pll_settings *pll_settings)
 {
        struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
+       struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
        uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
 
        if (pix_clk_params == NULL || pll_settings == NULL
                        || pix_clk_params->requested_pix_clk == 0) {
-               DC_LOG_ERROR(clk_src->base.ctx->logger,
+               DC_LOG_ERROR(
                        "%s: Invalid parameters!!\n", __func__);
                return pll_calc_error;
        }
@@ -1052,14 +1054,14 @@ static void get_ss_info_from_atombios(
        struct spread_spectrum_info *ss_info_cur;
        struct spread_spectrum_data *ss_data_cur;
        uint32_t i;
-
+       struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll;
        if (ss_entries_num == NULL) {
-               DC_LOG_SYNC(clk_src->base.ctx->logger,
+               DC_LOG_SYNC(
                        "Invalid entry !!!\n");
                return;
        }
        if (spread_spectrum_data == NULL) {
-               DC_LOG_SYNC(clk_src->base.ctx->logger,
+               DC_LOG_SYNC(
                        "Invalid array pointer!!!\n");
                return;
        }
@@ -1104,7 +1106,7 @@ static void get_ss_info_from_atombios(
                ++i, ++ss_info_cur, ++ss_data_cur) {
 
                if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
-                       DC_LOG_SYNC(clk_src->base.ctx->logger,
+                       DC_LOG_SYNC(
                                "Invalid ATOMBIOS SS Table!!!\n");
                        goto out_free_data;
                }
@@ -1114,9 +1116,9 @@ static void get_ss_info_from_atombios(
                if (as_signal == AS_SIGNAL_TYPE_HDMI
                                && ss_info_cur->spread_spectrum_percentage > 6){
                        /* invalid input, do nothing */
-                       DC_LOG_SYNC(clk_src->base.ctx->logger,
+                       DC_LOG_SYNC(
                                "Invalid SS percentage ");
-                       DC_LOG_SYNC(clk_src->base.ctx->logger,
+                       DC_LOG_SYNC(
                                "for HDMI in ATOMBIOS info Table!!!\n");
                        continue;
                }
@@ -1228,12 +1230,12 @@ static bool calc_pll_max_vco_construct(
        if (init_data->num_fract_fb_divider_decimal_point == 0 ||
                init_data->num_fract_fb_divider_decimal_point_precision >
                                init_data->num_fract_fb_divider_decimal_point) {
-               DC_LOG_ERROR(calc_pll_cs->ctx->logger,
+               DC_LOG_ERROR(
                        "The dec point num or precision is incorrect!");
                return false;
        }
        if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
-               DC_LOG_ERROR(calc_pll_cs->ctx->logger,
+               DC_LOG_ERROR(
                        "Incorrect fract feedback divider precision num!");
                return false;
        }