drm/amd/display: Add link encoder dp_ycbcr420_supported feature flag

[linux.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_resource.c

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index affadd7bfe8d1cc7c71c7e520af89bef3274a6ff..3d9118e1ee105fc1aeee84fb357d926f916dbd11 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -40,7 +40,7 @@
 #include "dcn10/dcn10_opp.h"
 #include "dcn10/dcn10_link_encoder.h"
 #include "dcn10/dcn10_stream_encoder.h"
-#include "dce/dce_clocks.h"
+#include "dcn10/dcn10_dccg.h"
 #include "dce/dce_clock_source.h"
 #include "dce/dce_audio.h"
 #include "dce/dce_hwseq.h"
@@ -507,6 +507,18 @@ static const struct resource_caps res_cap = {
                .num_ddc = 4,
 };
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+static const struct resource_caps rv2_res_cap = {
+               .num_timing_generator = 3,
+               .num_opp = 3,
+               .num_video_plane = 3,
+               .num_audio = 3,
+               .num_stream_encoder = 3,
+               .num_pll = 3,
+               .num_ddc = 3,
+};
+#endif
+
 static const struct dc_debug_options debug_defaults_drv = {
                .sanity_checks = true,
                .disable_dmcu = true,
@@ -707,7 +719,8 @@ static struct timing_generator *dcn10_timing_generator_create(
 static const struct encoder_feature_support link_enc_feature = {
                .max_hdmi_deep_color = COLOR_DEPTH_121212,
                .max_hdmi_pixel_clock = 600000,
-               .ycbcr420_supported = true,
+               .hdmi_ycbcr420_supported = true,
+               .dp_ycbcr420_supported = false,
                .flags.bits.IS_HBR2_CAPABLE = true,
                .flags.bits.IS_HBR3_CAPABLE = true,
                .flags.bits.IS_TPS3_CAPABLE = true,
@@ -896,7 +909,9 @@ static void destruct(struct dcn10_resource_pool *pool)
                        kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
                        pool->base.timing_generators[i] = NULL;
                }
+       }
 
+       for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
                if (pool->base.engines[i] != NULL)
                        pool->base.engines[i]->funcs->destroy_engine(&pool->base.engines[i]);
                if (pool->base.hw_i2cs[i] != NULL) {
@@ -1170,7 +1185,12 @@ static bool construct(
 
        ctx->dc_bios->regs = &bios_regs;
 
-       pool->base.res_cap = &res_cap;
+#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
+       if (ctx->dce_version == DCN_VERSION_1_01)
+               pool->base.res_cap = &rv2_res_cap;
+       else
+#endif
+               pool->base.res_cap = &res_cap;
        pool->base.funcs = &dcn10_res_pool_funcs;
 
        /*