AMD_IP_BLOCK_TYPE_UVD,
AMD_IP_BLOCK_TYPE_VCE,
AMD_IP_BLOCK_TYPE_ACP,
- AMD_IP_BLOCK_TYPE_VCN
+ AMD_IP_BLOCK_TYPE_VCN,
+ AMD_IP_BLOCK_TYPE_MES
};
enum amd_clockgating_state {
#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24)
+#define AMD_CG_SUPPORT_HDP_DS (1 << 25)
+#define AMD_CG_SUPPORT_HDP_SD (1 << 26)
+#define AMD_CG_SUPPORT_IH_CG (1 << 27)
+#define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
+#define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
#define AMD_PG_SUPPORT_MMHUB (1 << 13)
#define AMD_PG_SUPPORT_VCN (1 << 14)
-#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
+#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
+#define AMD_PG_SUPPORT_ATHUB (1 << 16)
enum PP_FEATURE_MASK {
PP_SCLK_DPM_MASK = 0x1,