drm/amd/powerplay: cache the watermark settings on system memory

[linux.git] / drivers / gpu / drm / amd / powerplay / inc / amdgpu_smu.h

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ca3fdc6777cf00cbf8e5611b6b44bdbdb923adac..02d33b50e735281540168318560a02d29e592e8f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -254,6 +254,7 @@ struct smu_table_context
        unsigned long                   metrics_time;
        void                            *metrics_table;
        void                            *clocks_table;
+       void                            *watermarks_table;
 
        void                            *max_sustainable_clocks;
        struct smu_bios_boot_up_values  boot_values;
@@ -350,6 +351,7 @@ struct smu_context
        const struct pptable_funcs      *ppt_funcs;
        struct mutex                    mutex;
        struct mutex                    sensor_lock;
+       struct mutex                    metrics_lock;
        uint64_t pool_size;
 
        struct smu_table_context        smu_table;
@@ -443,7 +445,7 @@ struct pptable_funcs {
        int (*pre_display_config_changed)(struct smu_context *smu);
        int (*display_config_changed)(struct smu_context *smu);
        int (*apply_clocks_adjust_rules)(struct smu_context *smu);
-       int (*notify_smc_dispaly_config)(struct smu_context *smu);
+       int (*notify_smc_display_config)(struct smu_context *smu);
        int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
        int (*unforce_dpm_levels)(struct smu_context *smu);
        int (*get_profiling_clk_mask)(struct smu_context *smu,
@@ -696,6 +698,8 @@ int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max);
 int smu_set_hard_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
                            uint32_t min, uint32_t max);
+int smu_get_dpm_level_range(struct smu_context *smu, enum smu_clk_type clk_type,
+                           uint32_t *min_value, uint32_t *max_value);
 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level);
 int smu_set_display_count(struct smu_context *smu, uint32_t count);