drm/amdgpu/smu: custom pstate profiling clock frequence for navi series asics

[linux.git] / drivers / gpu / drm / amd / powerplay / navi10_ppt.c

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 7b42e72dc939fbe8c4dee8f1789109a84a866948..455f1ef23ab8017efc659f097e88947387065fd8 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -564,17 +564,20 @@ static int navi10_get_metrics_table(struct smu_context *smu,
        struct smu_table_context *smu_table= &smu->smu_table;
        int ret = 0;
 
+       mutex_lock(&smu->metrics_lock);
        if (!smu_table->metrics_time || time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(100))) {
                ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, 0,
                                (void *)smu_table->metrics_table, false);
                if (ret) {
                        pr_info("Failed to export SMU metrics table!\n");
+                       mutex_unlock(&smu->metrics_lock);
                        return ret;
                }
                smu_table->metrics_time = jiffies;
        }
 
        memcpy(metrics_table, smu_table->metrics_table, sizeof(SmuMetrics_t));
+       mutex_unlock(&smu->metrics_lock);
 
        return ret;
 }
@@ -1579,12 +1582,44 @@ static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_
        return 0;
 }
 
-static int navi10_set_peak_clock_by_device(struct smu_context *smu)
+static int navi10_set_performance_level(struct smu_context *smu,
+                                       enum amd_dpm_forced_level level);
+
+static int navi10_set_standard_performance_level(struct smu_context *smu)
+{
+       struct amdgpu_device *adev = smu->adev;
+       int ret = 0;
+       uint32_t sclk_freq = 0, uclk_freq = 0;
+
+       switch (adev->asic_type) {
+       case CHIP_NAVI10:
+               sclk_freq = NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
+               uclk_freq = NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
+               break;
+       case CHIP_NAVI14:
+               sclk_freq = NAVI14_UMD_PSTATE_PROFILING_GFXCLK;
+               uclk_freq = NAVI14_UMD_PSTATE_PROFILING_MEMCLK;
+               break;
+       default:
+               /* by default, this is same as auto performance level */
+               return navi10_set_performance_level(smu, AMD_DPM_FORCED_LEVEL_AUTO);
+       }
+
+       ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
+       if (ret)
+               return ret;
+       ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
+       if (ret)
+               return ret;
+
+       return ret;
+}
+
+static int navi10_set_peak_performance_level(struct smu_context *smu)
 {
        struct amdgpu_device *adev = smu->adev;
        int ret = 0;
        uint32_t sclk_freq = 0, uclk_freq = 0;
-       uint32_t uclk_level = 0;
 
        switch (adev->asic_type) {
        case CHIP_NAVI10:
@@ -1625,14 +1660,16 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
                        break;
                }
                break;
+       case CHIP_NAVI12:
+               sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
+               break;
        default:
-               return -EINVAL;
+               ret = smu_get_dpm_level_range(smu, SMU_SCLK, NULL, &sclk_freq);
+               if (ret)
+                       return ret;
        }
 
-       ret = smu_get_dpm_level_count(smu, SMU_UCLK, &uclk_level);
-       if (ret)
-               return ret;
-       ret = smu_get_dpm_freq_by_index(smu, SMU_UCLK, uclk_level - 1, &uclk_freq);
+       ret = smu_get_dpm_level_range(smu, SMU_UCLK, NULL, &uclk_freq);
        if (ret)
                return ret;
 
@@ -1646,19 +1683,45 @@ static int navi10_set_peak_clock_by_device(struct smu_context *smu)
        return ret;
 }
 
-static int navi10_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+static int navi10_set_performance_level(struct smu_context *smu,
+                                       enum amd_dpm_forced_level level)
 {
        int ret = 0;
+       uint32_t sclk_mask, mclk_mask, soc_mask;
 
        switch (level) {
+       case AMD_DPM_FORCED_LEVEL_HIGH:
+               ret = smu_force_dpm_limit_value(smu, true);
+               break;
+       case AMD_DPM_FORCED_LEVEL_LOW:
+               ret = smu_force_dpm_limit_value(smu, false);
+               break;
+       case AMD_DPM_FORCED_LEVEL_AUTO:
+               ret = smu_unforce_dpm_levels(smu);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
+               ret = navi10_set_standard_performance_level(smu);
+               break;
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
+               ret = smu_get_profiling_clk_mask(smu, level,
+                                                &sclk_mask,
+                                                &mclk_mask,
+                                                &soc_mask);
+               if (ret)
+                       return ret;
+               smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask, false);
+               smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask, false);
+               smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask, false);
+               break;
        case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-               ret = navi10_set_peak_clock_by_device(smu);
+               ret = navi10_set_peak_performance_level(smu);
                break;
+       case AMD_DPM_FORCED_LEVEL_MANUAL:
+       case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
        default:
-               ret = -EINVAL;
                break;
        }
-
        return ret;
 }