]> asedeno.scripts.mit.edu Git - linux.git/blobdiff - drivers/gpu/drm/amd/powerplay/vega20_ppt.c
drm/amd/powerplay: avoid access before allocation
[linux.git] / drivers / gpu / drm / amd / powerplay / vega20_ppt.c
index 0f14fe14ecd845d335b551477d33fea5d6d08bb2..6d267aeacda37072a201a45006a3db41fc66ea70 100644 (file)
@@ -319,7 +319,7 @@ static int vega20_tables_init(struct smu_context *smu, struct smu_table *tables)
                       AMDGPU_GEM_DOMAIN_VRAM);
 
        smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
-       if (smu_table->metrics_table)
+       if (!smu_table->metrics_table)
                return -ENOMEM;
        smu_table->metrics_time = 0;
 
@@ -441,7 +441,6 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
 {
        ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
        struct smu_table_context *table_context = &smu->smu_table;
-       int ret;
 
        if (!table_context->power_play_table)
                return -EINVAL;
@@ -455,9 +454,7 @@ static int vega20_store_powerplay_table(struct smu_context *smu)
        table_context->thermal_controller_type = powerplay_table->ucThermalControllerType;
        table_context->TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
 
-       ret = vega20_setup_od8_information(smu);
-
-       return ret;
+       return 0;
 }
 
 static int vega20_append_powerplay_table(struct smu_context *smu)
@@ -992,7 +989,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_SOCCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_SOCCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_SOCCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current socclk Failed!");
                        return ret;
@@ -1013,7 +1010,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_FCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_FCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_FCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current fclk Failed!");
                        return ret;
@@ -1028,7 +1025,7 @@ static int vega20_print_clk_levels(struct smu_context *smu,
                break;
 
        case SMU_DCEFCLK:
-               ret = smu_get_current_clk_freq(smu, PPCLK_DCEFCLK, &now);
+               ret = smu_get_current_clk_freq(smu, SMU_DCEFCLK, &now);
                if (ret) {
                        pr_err("Attempt to get current dcefclk Failed!");
                        return ret;
@@ -1502,11 +1499,17 @@ static int vega20_set_default_od8_setttings(struct smu_context *smu)
 
        od8_settings = kzalloc(sizeof(struct vega20_od8_settings), GFP_KERNEL);
 
-       if (od8_settings)
+       if (!od8_settings)
                return -ENOMEM;
 
        smu->od_settings = (void *)od8_settings;
 
+       ret = vega20_setup_od8_information(smu);
+       if (ret) {
+               pr_err("Retrieve board OD limits failed!\n");
+               return ret;
+       }
+
        if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
                if (od8_settings->od_feature_capabilities[ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS] &&
                    od8_settings->od_settings_max[OD8_SETTING_GFXCLK_FMAX] > 0 &&
@@ -3016,15 +3019,17 @@ static int vega20_get_fan_speed_percent(struct smu_context *smu,
                                        uint32_t *speed)
 {
        int ret = 0;
-       uint32_t percent = 0;
-       uint32_t current_rpm;
+       uint32_t current_rpm = 0, percent = 0;
        PPTable_t *pptable = smu->smu_table.driver_pptable;
 
        ret = smu_get_current_rpm(smu, &current_rpm);
+       if (ret)
+               return ret;
+
        percent = current_rpm * 100 / pptable->FanMaximumRpm;
        *speed = percent > 100 ? 100 : percent;
 
-       return ret;
+       return 0;
 }
 
 static int vega20_get_gpu_power(struct smu_context *smu, uint32_t *value)