drm/i915/gvt: Fix PTE write flush for taking runtime pm properly

[linux.git] / drivers / gpu / drm / i915 / gvt / gtt.c

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 69d3d8ddecc25846cb47d064f2d165a54526fac5..acbe3f2ad6fc5b019b9f0fa10ee2f8ac4874cf6a 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -2290,12 +2290,15 @@ void intel_gvt_clean_gtt(struct intel_gvt *gvt)
 void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
 {
        struct intel_gvt *gvt = vgpu->gvt;
+       struct drm_i915_private *dev_priv = gvt->dev_priv;
        struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
        u32 index;
        u32 offset;
        u32 num_entries;
        struct intel_gvt_gtt_entry e;
 
+       intel_runtime_pm_get(dev_priv);
+
        memset(&e, 0, sizeof(struct intel_gvt_gtt_entry));
        e.type = GTT_TYPE_GGTT_PTE;
        ops->set_pfn(&e, gvt->gtt.scratch_ggtt_mfn);
@@ -2310,6 +2313,8 @@ void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu)
        num_entries = vgpu_hidden_sz(vgpu) >> PAGE_SHIFT;
        for (offset = 0; offset < num_entries; offset++)
                ops->set_entry(NULL, &e, index + offset, false, 0, vgpu);
+
+       intel_runtime_pm_put(dev_priv);
 }
 
 /**