Merge tag 'mips_fixes_4.16_2' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan...

[linux.git] / drivers / gpu / drm / i915 / gvt / mmio_context.c

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 74834395dd892d2f78eacd22499dd868586a03cf..256f1bb522b7a2edb5490c81be29aa46774e3ed1 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -80,7 +80,7 @@ static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
        {BCS, RING_INSTPM(BLT_RING_BASE), 0xffff, false}, /* 0x220c0 */
        {BCS, RING_HWSTAM(BLT_RING_BASE), 0x0, false}, /* 0x22098 */
        {BCS, RING_EXCC(BLT_RING_BASE), 0x0, false}, /* 0x22028 */
-       { /* Terminated */ }
+       {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
 };
 
 static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
@@ -118,6 +118,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
        {RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
        {RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
        {RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
+       {RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
        {RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */
        {RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */
        {RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */
@@ -146,7 +147,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
        {RCS, GEN8_GARBCNTL, 0x0, false}, /* 0xb004 */
        {RCS, GEN7_FF_THREAD_MODE, 0x0, false}, /* 0x20a0 */
        {RCS, FF_SLICE_CS_CHICKEN2, 0xffff, false}, /* 0x20e4 */
-       { /* Terminated */ }
+       {RCS, INVALID_MMIO_REG, 0, false } /* Terminated */
 };
 
 static struct {
@@ -167,7 +168,7 @@ static void load_render_mocs(struct drm_i915_private *dev_priv)
        };
        int ring_id, i;
 
-       for (ring_id = 0; ring_id < I915_NUM_ENGINES; ring_id++) {
+       for (ring_id = 0; ring_id < ARRAY_SIZE(regs); ring_id++) {
                offset.reg = regs[ring_id];
                for (i = 0; i < 64; i++) {
                        gen9_render_mocs.control_table[ring_id][i] =
@@ -310,8 +311,8 @@ static void switch_mmio(struct intel_vgpu *pre,
        if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
                switch_mocs(pre, next, ring_id);
 
-       mmio = dev_priv->gvt->engine_mmio_list;
-       while (i915_mmio_reg_offset((mmio++)->reg)) {
+       for (mmio = dev_priv->gvt->engine_mmio_list;
+            i915_mmio_reg_valid(mmio->reg); mmio++) {
                if (mmio->ring_id != ring_id)
                        continue;
                // save