drm/i915/guc: Skip suspend/resume GuC action on platforms w/o GuC submission

[linux.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e6118f62b29a465c4305920797e49ddabafa57c..bbf4dfdfa8ba025cb0f7b57cc2bc00d9471270d9 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -627,13 +627,9 @@ struct ddi_vbt_port_info {
 
        int max_tmds_clock;
 
-       /*
-        * This is an index in the HDMI/DVI DDI buffer translation table.
-        * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
-        * populate this field.
-        */
-#define HDMI_LEVEL_SHIFT_UNKNOWN       0xff
+       /* This is an index in the HDMI/DVI DDI buffer translation table. */
        u8 hdmi_level_shift;
+       u8 hdmi_level_shift_set:1;
 
        u8 supports_dvi:1;
        u8 supports_hdmi:1;
@@ -724,8 +720,7 @@ struct intel_vbt_data {
 
        int crt_ddc_pin;
 
-       int child_dev_num;
-       struct child_device_config *child_dev;
+       struct list_head display_devices;
 
        struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
        struct sdvo_device_mapping sdvo_mappings[2];
@@ -891,6 +886,10 @@ struct intel_cdclk_state {
        u8 voltage_level;
 };
 
+struct i915_selftest_stash {
+       atomic_t counter;
+};
+
 struct drm_i915_private {
        struct drm_device drm;
 
@@ -1248,8 +1247,6 @@ struct drm_i915_private {
        struct intel_gt gt;
 
        struct {
-               struct notifier_block pm_notifier;
-
                struct i915_gem_contexts {
                        spinlock_t lock; /* locks list */
                        struct list_head list;
@@ -1286,6 +1283,8 @@ struct drm_i915_private {
        /* Mutex to protect the above hdcp component related values. */
        struct mutex hdcp_comp_mutex;
 
+       I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
+
        /*
         * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
         * will be rejected. Instead look for a better place.
@@ -1614,9 +1613,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define VEBOX_MASK(dev_priv) \
        ENGINE_INSTANCES_MASK(dev_priv, VECS0, I915_MAX_VECS)
 
+/*
+ * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
+ * All later gens can run the final buffer from the ppgtt
+ */
+#define CMDPARSER_USES_GGTT(dev_priv) IS_GEN(dev_priv, 7)
+
 #define HAS_LLC(dev_priv)      (INTEL_INFO(dev_priv)->has_llc)
 #define HAS_SNOOP(dev_priv)    (INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)    ((dev_priv)->edram_size_mb)
+#define HAS_SECURE_BATCHES(dev_priv) (INTEL_GEN(dev_priv) < 6)
 #define HAS_WT(dev_priv)       ((IS_HASWELL(dev_priv) || \
                                 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
 
@@ -1649,10 +1655,12 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
 #define HAS_BROKEN_CS_TLB(dev_priv)    (IS_I830(dev_priv) || IS_I845G(dev_priv))
 
+#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)  \
+       (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9))
+
 /* WaRsDisableCoarsePowerGating:skl,cnl */
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
-       (IS_CANNONLAKE(dev_priv) || \
-        IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
+       IS_GEN_RANGE(dev_priv, 9, 10)
 
 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
@@ -1779,7 +1787,6 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
 /* i915_gem.c */
 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
-void i915_gem_sanitize(struct drm_i915_private *i915);
 void i915_gem_init_early(struct drm_i915_private *dev_priv);
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
 int i915_gem_freeze(struct drm_i915_private *dev_priv);
@@ -1863,7 +1870,6 @@ static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
        return atomic_read(&error->reset_engine_count[engine->uabi_class]);
 }
 
-void i915_gem_init_mmio(struct drm_i915_private *i915);
 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
 void i915_gem_driver_register(struct drm_i915_private *i915);
 void i915_gem_driver_unregister(struct drm_i915_private *i915);
@@ -1941,12 +1947,14 @@ const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
-int intel_engine_cmd_parser(struct intel_engine_cs *engine,
+int intel_engine_cmd_parser(struct i915_gem_context *cxt,
+                           struct intel_engine_cs *engine,
                            struct drm_i915_gem_object *batch_obj,
-                           struct drm_i915_gem_object *shadow_batch_obj,
+                           u64 user_batch_start,
                            u32 batch_start_offset,
                            u32 batch_len,
-                           bool is_master);
+                           struct drm_i915_gem_object *shadow_batch_obj,
+                           u64 shadow_batch_start);
 
 /* intel_device_info.c */
 static inline struct intel_device_info *
@@ -2028,4 +2036,10 @@ i915_coherent_map_type(struct drm_i915_private *i915)
        return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 }
 
+static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
+{
+       return intel_guc_is_submission_supported(guc) &&
+               intel_guc_is_running(guc);
+}
+
 #endif