drm/i915/cnl: Implement CNL display init/unit sequence

[linux.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac3df675b4f370026d68d5dbcfd988ca7da9044a..539e44e88e01bff694c4c66f8e9af2b209a9b00c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1661,6 +1661,9 @@ enum skl_disp_power_wells {
 #define   PHY_RESERVED                 (1 << 7)
 #define BXT_PORT_CL1CM_DW0(phy)                _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
 
+#define CNL_PORT_CL1CM_DW5             _MMIO(0x162014)
+#define   CL_POWER_DOWN_ENABLE         (1 << 4)
+
 #define _PORT_CL1CM_DW9_A              0x162024
 #define _PORT_CL1CM_DW9_BC             0x6C024
 #define   IREF0RC_OFFSET_SHIFT         8
@@ -1693,6 +1696,23 @@ enum skl_disp_power_wells {
 #define BXT_PORT_CL2CM_DW6(phy)                _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
 #define   DW6_OLDO_DYN_PWR_DOWN_EN     (1 << 28)
 
+#define CNL_PORT_COMP_DW0              _MMIO(0x162100)
+#define   COMP_INIT                    (1 << 31)
+#define CNL_PORT_COMP_DW1              _MMIO(0x162104)
+#define CNL_PORT_COMP_DW3              _MMIO(0x16210c)
+#define   PROCESS_INFO_DOT_0           (0 << 26)
+#define   PROCESS_INFO_DOT_1           (1 << 26)
+#define   PROCESS_INFO_DOT_4           (2 << 26)
+#define   PROCESS_INFO_MASK            (7 << 26)
+#define   PROCESS_INFO_SHIFT           26
+#define   VOLTAGE_INFO_0_85V           (0 << 24)
+#define   VOLTAGE_INFO_0_95V           (1 << 24)
+#define   VOLTAGE_INFO_1_05V           (2 << 24)
+#define   VOLTAGE_INFO_MASK            (3 << 24)
+#define   VOLTAGE_INFO_SHIFT           24
+#define CNL_PORT_COMP_DW9              _MMIO(0x162124)
+#define CNL_PORT_COMP_DW10             _MMIO(0x162128)
+
 /* BXT PHY Ref registers */
 #define _PORT_REF_DW3_A                        0x16218C
 #define _PORT_REF_DW3_BC               0x6C18C
@@ -6510,6 +6530,9 @@ enum {
 #define  GLK_CL1_PWR_DOWN      (1 << 11)
 #define  GLK_CL2_PWR_DOWN      (1 << 12)
 
+#define CHICKEN_MISC_2         _MMIO(0x42084)
+#define  COMP_PWR_DOWN         (1 << 23)
+
 #define _CHICKEN_PIPESL_1_A    0x420b0
 #define _CHICKEN_PIPESL_1_B    0x420b4
 #define  HSW_FBCQ_DIS                  (1 << 22)