drm/i915: take a reference to uncore in the engine and use it

[linux.git] / drivers / gpu / drm / i915 / intel_lrc.c

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 66bc3cd4e1669a796ae693ac1bf810a05114738d..3870215061997e29c5251d6f940803c42fbc741f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2074,16 +2074,14 @@ static int gen8_emit_bb_start(struct i915_request *rq,
 
 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
 {
-       struct drm_i915_private *dev_priv = engine->i915;
-       I915_WRITE_IMR(engine,
-                      ~(engine->irq_enable_mask | engine->irq_keep_mask));
-       POSTING_READ_FW(RING_IMR(engine->mmio_base));
+       ENGINE_WRITE(engine, RING_IMR,
+                    ~(engine->irq_enable_mask | engine->irq_keep_mask));
+       ENGINE_POSTING_READ(engine, RING_IMR);
 }
 
 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
 {
-       struct drm_i915_private *dev_priv = engine->i915;
-       I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
+       ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
 }
 
 static int gen8_emit_flush(struct i915_request *request, u32 mode)
@@ -2288,7 +2286,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
        dev_priv = engine->i915;
 
        if (engine->buffer) {
-               WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
+               WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
        }
 
        if (engine->cleanup)
@@ -2400,6 +2398,7 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *i915 = engine->i915;
        struct intel_engine_execlists * const execlists = &engine->execlists;
+       u32 base = engine->mmio_base;
        int ret;
 
        ret = intel_engine_init_common(engine);
@@ -2410,12 +2409,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 
        if (HAS_LOGICAL_RING_ELSQ(i915)) {
                execlists->submit_reg = i915->uncore.regs +
-                       i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
+                       i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
                execlists->ctrl_reg = i915->uncore.regs +
-                       i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
+                       i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
        } else {
                execlists->submit_reg = i915->uncore.regs +
-                       i915_mmio_reg_offset(RING_ELSP(engine));
+                       i915_mmio_reg_offset(RING_ELSP(base));
        }
 
        execlists->preempt_complete_status = ~0u;
@@ -2658,7 +2657,7 @@ static void execlists_init_reg_state(u32 *regs,
        regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
                                 MI_LRI_FORCE_POSTED;
 
-       CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
+       CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
                _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
                _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
        if (INTEL_GEN(engine->i915) < 11) {