iommu/vt-d: Replace Intel specific PASID allocator with IOASID

[linux.git] / drivers / iommu / intel-pasid.c

diff --git a/drivers/iommu/intel-pasid.c b/drivers/iommu/intel-pasid.c
index 040a445be30091f4a7cbf6c2158ff9c69896b399..3cb569e76642358028a6cef3f43e508b9e4e2c4e 100644 (file)
--- a/drivers/iommu/intel-pasid.c
+++ b/drivers/iommu/intel-pasid.c
@@ -26,42 +26,6 @@
  */
 static DEFINE_SPINLOCK(pasid_lock);
 u32 intel_pasid_max_id = PASID_MAX;
-static DEFINE_IDR(pasid_idr);
-
-int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp)
-{
-       int ret, min, max;
-
-       min = max_t(int, start, PASID_MIN);
-       max = min_t(int, end, intel_pasid_max_id);
-
-       WARN_ON(in_interrupt());
-       idr_preload(gfp);
-       spin_lock(&pasid_lock);
-       ret = idr_alloc(&pasid_idr, ptr, min, max, GFP_ATOMIC);
-       spin_unlock(&pasid_lock);
-       idr_preload_end();
-
-       return ret;
-}
-
-void intel_pasid_free_id(int pasid)
-{
-       spin_lock(&pasid_lock);
-       idr_remove(&pasid_idr, pasid);
-       spin_unlock(&pasid_lock);
-}
-
-void *intel_pasid_lookup_id(int pasid)
-{
-       void *p;
-
-       spin_lock(&pasid_lock);
-       p = idr_find(&pasid_idr, pasid);
-       spin_unlock(&pasid_lock);
-
-       return p;
-}
 
 /*
  * Per device pasid table management:
@@ -465,6 +429,21 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu,
                devtlb_invalidation_with_pasid(iommu, dev, pasid);
 }
 
+static void pasid_flush_caches(struct intel_iommu *iommu,
+                               struct pasid_entry *pte,
+                               int pasid, u16 did)
+{
+       if (!ecap_coherent(iommu->ecap))
+               clflush_cache_range(pte, sizeof(*pte));
+
+       if (cap_caching_mode(iommu->cap)) {
+               pasid_cache_invalidation_with_pasid(iommu, did, pasid);
+               iotlb_invalidation_with_pasid(iommu, did, pasid);
+       } else {
+               iommu_flush_write_buffer(iommu);
+       }
+}
+
 /*
  * Set up the scalable mode pasid table entry for first only
  * translation type.
@@ -499,8 +478,16 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
        }
 
 #ifdef CONFIG_X86
-       if (cpu_feature_enabled(X86_FEATURE_LA57))
-               pasid_set_flpm(pte, 1);
+       /* Both CPU and IOMMU paging mode need to match */
+       if (cpu_feature_enabled(X86_FEATURE_LA57)) {
+               if (cap_5lp_support(iommu->cap)) {
+                       pasid_set_flpm(pte, 1);
+               } else {
+                       pr_err("VT-d has no 5-level paging support for CPU\n");
+                       pasid_clear_entry(pte);
+                       return -EINVAL;
+               }
+       }
 #endif /* CONFIG_X86 */
 
        pasid_set_domain_id(pte, did);
@@ -510,16 +497,7 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu,
        /* Setup Present and PASID Granular Transfer Type: */
        pasid_set_translation_type(pte, 1);
        pasid_set_present(pte);
-
-       if (!ecap_coherent(iommu->ecap))
-               clflush_cache_range(pte, sizeof(*pte));
-
-       if (cap_caching_mode(iommu->cap)) {
-               pasid_cache_invalidation_with_pasid(iommu, did, pasid);
-               iotlb_invalidation_with_pasid(iommu, did, pasid);
-       } else {
-               iommu_flush_write_buffer(iommu);
-       }
+       pasid_flush_caches(iommu, pte, pasid, did);
 
        return 0;
 }
@@ -583,16 +561,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu,
         */
        pasid_set_sre(pte);
        pasid_set_present(pte);
-
-       if (!ecap_coherent(iommu->ecap))
-               clflush_cache_range(pte, sizeof(*pte));
-
-       if (cap_caching_mode(iommu->cap)) {
-               pasid_cache_invalidation_with_pasid(iommu, did, pasid);
-               iotlb_invalidation_with_pasid(iommu, did, pasid);
-       } else {
-               iommu_flush_write_buffer(iommu);
-       }
+       pasid_flush_caches(iommu, pte, pasid, did);
 
        return 0;
 }
@@ -626,16 +595,7 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu,
         */
        pasid_set_sre(pte);
        pasid_set_present(pte);
-
-       if (!ecap_coherent(iommu->ecap))
-               clflush_cache_range(pte, sizeof(*pte));
-
-       if (cap_caching_mode(iommu->cap)) {
-               pasid_cache_invalidation_with_pasid(iommu, did, pasid);
-               iotlb_invalidation_with_pasid(iommu, did, pasid);
-       } else {
-               iommu_flush_write_buffer(iommu);
-       }
+       pasid_flush_caches(iommu, pte, pasid, did);
 
        return 0;
 }