Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

[linux.git] / drivers / iommu / qcom_iommu.c

diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 52f38292df5b634e6c25adf56649b90eef76610e..39759db4f0038c0ec7dd49928b75e6d89e5cae86 100644 (file)
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -201,7 +201,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
 
        fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
 
-       if (!(fsr & FSR_FAULT))
+       if (!(fsr & ARM_SMMU_FSR_FAULT))
                return IRQ_NONE;
 
        fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
@@ -215,7 +215,7 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
        }
 
        iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
-       iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE);
+       iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
 
        return IRQ_HANDLED;
 }
@@ -269,18 +269,15 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
 
                /* TTBRs */
                iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
-                               pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] |
-                               FIELD_PREP(TTBRn_ASID, ctx->asid));
-               iommu_writeq(ctx, ARM_SMMU_CB_TTBR1,
-                               pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] |
-                               FIELD_PREP(TTBRn_ASID, ctx->asid));
+                               pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
+                               FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
+               iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
 
                /* TCR */
                iommu_writel(ctx, ARM_SMMU_CB_TCR2,
-                               (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
-                               FIELD_PREP(TCR2_SEP, TCR2_SEP_UPSTREAM));
+                               arm_smmu_lpae_tcr2(&pgtbl_cfg));
                iommu_writel(ctx, ARM_SMMU_CB_TCR,
-                               pgtbl_cfg.arm_lpae_s1_cfg.tcr);
+                            arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
 
                /* MAIRs (stage-1 only) */
                iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
@@ -289,11 +286,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
                                pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
 
                /* SCTLR */
-               reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
-                       SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG;
+               reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
+                     ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
+                     ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
+                     ARM_SMMU_SCTLR_CFCFG;
 
                if (IS_ENABLED(CONFIG_BIG_ENDIAN))
-                       reg |= SCTLR_E;
+                       reg |= ARM_SMMU_SCTLR_E;
 
                iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);