drm/bridge: Make the bridge chain a double-linked list

[linux.git] / drivers / irqchip / irq-gic-common.c

diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c
index b0a8215a13fc086958932f96557d1c1113022c40..82520006195de1aa5f6914cf7c34f0fdd0b8ba7b 100644 (file)
--- a/drivers/irqchip/irq-gic-common.c
+++ b/drivers/irqchip/irq-gic-common.c
@@ -41,6 +41,8 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
                void *data)
 {
        for (; quirks->desc; quirks++) {
+               if (quirks->compatible)
+                       continue;
                if (quirks->iidr != (quirks->mask & iidr))
                        continue;
                if (quirks->init(data))
@@ -63,7 +65,7 @@ int gic_configure_irq(unsigned int irq, unsigned int type,
         * for "irq", depending on "type".
         */
        raw_spin_lock_irqsave(&irq_controller_lock, flags);
-       val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
+       val = oldval = readl_relaxed(base + confoff);
        if (type & IRQ_TYPE_LEVEL_MASK)
                val &= ~confmask;
        else if (type & IRQ_TYPE_EDGE_BOTH)
@@ -83,14 +85,10 @@ int gic_configure_irq(unsigned int irq, unsigned int type,
         * does not allow us to set the configuration or we are in a
         * non-secure mode, and hence it may not be catastrophic.
         */
-       writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
-       if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val) {
-               if (WARN_ON(irq >= 32))
-                       ret = -EINVAL;
-               else
-                       pr_warn("GIC: PPI%d is secure or misconfigured\n",
-                               irq - 16);
-       }
+       writel_relaxed(val, base + confoff);
+       if (readl_relaxed(base + confoff) != val)
+               ret = -EINVAL;
+
        raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
 
        if (sync_access)
@@ -132,26 +130,31 @@ void gic_dist_config(void __iomem *base, int gic_irqs,
                sync_access();
 }
 
-void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
+void gic_cpu_config(void __iomem *base, int nr, void (*sync_access)(void))
 {
        int i;
 
        /*
         * Deal with the banked PPI and SGI interrupts - disable all
-        * PPI interrupts, ensure all SGI interrupts are enabled.
-        * Make sure everything is deactivated.
+        * private interrupts. Make sure everything is deactivated.
         */
-       writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
-       writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
-       writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
+       for (i = 0; i < nr; i += 32) {
+               writel_relaxed(GICD_INT_EN_CLR_X32,
+                              base + GIC_DIST_ACTIVE_CLEAR + i / 8);
+               writel_relaxed(GICD_INT_EN_CLR_X32,
+                              base + GIC_DIST_ENABLE_CLEAR + i / 8);
+       }
 
        /*
         * Set priority on PPI and SGI interrupts
         */
-       for (i = 0; i < 32; i += 4)
+       for (i = 0; i < nr; i += 4)
                writel_relaxed(GICD_INT_DEF_PRI_X4,
                                        base + GIC_DIST_PRI + i * 4 / 4);
 
+       /* Ensure all SGI interrupts are now enabled */
+       writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
+
        if (sync_access)
                sync_access();
 }