irqchip/gic-v3: Dynamically allocate PPI NMI refcounts

[linux.git] / drivers / irqchip / irq-gic-v3.c

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index f884dd956ad614882d542ecb52e2ab3c1a2264b7..869a8056b0fc2230c83f63cb5cf70f800c08257b 100644 (file)
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -88,7 +88,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
 
 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
-static refcount_t ppi_nmi_refs[16];
+static refcount_t *ppi_nmi_refs;
 
 static struct gic_kvm_info gic_v3_kvm_info;
 static DEFINE_PER_CPU(bool, has_rss);
@@ -409,6 +409,16 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio)
        writeb_relaxed(prio, base + offset + index);
 }
 
+static u32 gic_get_ppi_index(struct irq_data *d)
+{
+       switch (get_intid_range(d)) {
+       case PPI_RANGE:
+               return d->hwirq - 16;
+       default:
+               unreachable();
+       }
+}
+
 static int gic_irq_nmi_setup(struct irq_data *d)
 {
        struct irq_desc *desc = irq_to_desc(d->irq);
@@ -429,10 +439,12 @@ static int gic_irq_nmi_setup(struct irq_data *d)
                return -EINVAL;
 
        /* desc lock should already be held */
-       if (gic_irq(d) < 32) {
+       if (gic_irq_in_rdist(d)) {
+               u32 idx = gic_get_ppi_index(d);
+
                /* Setting up PPI as NMI, only switch handler for first NMI */
-               if (!refcount_inc_not_zero(&ppi_nmi_refs[gic_irq(d) - 16])) {
-                       refcount_set(&ppi_nmi_refs[gic_irq(d) - 16], 1);
+               if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) {
+                       refcount_set(&ppi_nmi_refs[idx], 1);
                        desc->handle_irq = handle_percpu_devid_fasteoi_nmi;
                }
        } else {
@@ -464,9 +476,11 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
                return;
 
        /* desc lock should already be held */
-       if (gic_irq(d) < 32) {
+       if (gic_irq_in_rdist(d)) {
+               u32 idx = gic_get_ppi_index(d);
+
                /* Tearing down NMI, only switch handler for last NMI */
-               if (refcount_dec_and_test(&ppi_nmi_refs[gic_irq(d) - 16]))
+               if (refcount_dec_and_test(&ppi_nmi_refs[idx]))
                        desc->handle_irq = handle_percpu_devid_irq;
        } else {
                desc->handle_irq = handle_fasteoi_irq;
@@ -1394,7 +1408,19 @@ static void gic_enable_nmi_support(void)
 {
        int i;
 
-       for (i = 0; i < 16; i++)
+       if (!gic_prio_masking_enabled())
+               return;
+
+       if (gic_has_group0() && !gic_dist_security_disabled()) {
+               pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
+               return;
+       }
+
+       ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
+       if (!ppi_nmi_refs)
+               return;
+
+       for (i = 0; i < gic_data.ppi_nr; i++)
                refcount_set(&ppi_nmi_refs[i], 0);
 
        static_branch_enable(&supports_pseudo_nmis);
@@ -1472,12 +1498,7 @@ static int __init gic_init_bases(void __iomem *dist_base,
                        gicv2m_init(handle, gic_data.domain);
        }
 
-       if (gic_prio_masking_enabled()) {
-               if (!gic_has_group0() || gic_dist_security_disabled())
-                       gic_enable_nmi_support();
-               else
-                       pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
-       }
+       gic_enable_nmi_support();
 
        return 0;