ALSA: sparc: Constify snd_kcontrol_new items

[linux.git] / drivers / irqchip / irq-ingenic.c

diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index f126255b3260c7a05fc8d3b2493f3d3358ba51ec..01d18b39069ebee06224a451a5c1d5bee00533cf 100644 (file)
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
 /*
  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 platform IRQ support
+ *  Ingenic XBurst platform IRQ support
  */
 
 #include <linux/errno.h>
@@ -10,7 +10,6 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/irqchip.h>
-#include <linux/irqchip/ingenic.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/timex.h>
@@ -22,6 +21,7 @@
 
 struct ingenic_intc_data {
        void __iomem *base;
+       struct irq_domain *domain;
        unsigned num_chips;
 };
 
@@ -35,41 +35,30 @@ struct ingenic_intc_data {
 static irqreturn_t intc_cascade(int irq, void *data)
 {
        struct ingenic_intc_data *intc = irq_get_handler_data(irq);
-       uint32_t irq_reg;
+       struct irq_domain *domain = intc->domain;
+       struct irq_chip_generic *gc;
+       uint32_t pending;
        unsigned i;
 
        for (i = 0; i < intc->num_chips; i++) {
-               irq_reg = readl(intc->base + (i * CHIP_SIZE) +
-                               JZ_REG_INTC_PENDING);
-               if (!irq_reg)
+               gc = irq_get_domain_generic_chip(domain, i * 32);
+
+               pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING);
+               if (!pending)
                        continue;
 
-               generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+               while (pending) {
+                       int bit = __fls(pending);
+
+                       irq = irq_find_mapping(domain, bit + (i * 32));
+                       generic_handle_irq(irq);
+                       pending &= ~BIT(bit);
+               }
        }
 
        return IRQ_HANDLED;
 }
 
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
-{
-       struct irq_chip_regs *regs = &gc->chip_types->regs;
-
-       writel(mask, gc->reg_base + regs->enable);
-       writel(~mask, gc->reg_base + regs->disable);
-}
-
-void ingenic_intc_irq_suspend(struct irq_data *data)
-{
-       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-       intc_irq_set_mask(gc, gc->wake_active);
-}
-
-void ingenic_intc_irq_resume(struct irq_data *data)
-{
-       struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
-       intc_irq_set_mask(gc, gc->mask_cache);
-}
-
 static struct irqaction intc_cascade_action = {
        .handler = intc_cascade,
        .name = "SoC intc cascade interrupt",
@@ -108,17 +97,27 @@ static int __init ingenic_intc_of_init(struct device_node *node,
                goto out_unmap_irq;
        }
 
-       for (i = 0; i < num_chips; i++) {
-               /* Mask all irqs */
-               writel(0xffffffff, intc->base + (i * CHIP_SIZE) +
-                      JZ_REG_INTC_SET_MASK);
+       domain = irq_domain_add_legacy(node, num_chips * 32,
+                                      JZ4740_IRQ_BASE, 0,
+                                      &irq_generic_chip_ops, NULL);
+       if (!domain) {
+               err = -ENOMEM;
+               goto out_unmap_base;
+       }
 
-               gc = irq_alloc_generic_chip("INTC", 1,
-                                           JZ4740_IRQ_BASE + (i * 32),
-                                           intc->base + (i * CHIP_SIZE),
-                                           handle_level_irq);
+       intc->domain = domain;
+
+       err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC",
+                                            handle_level_irq, 0,
+                                            IRQ_NOPROBE | IRQ_LEVEL, 0);
+       if (err)
+               goto out_domain_remove;
+
+       for (i = 0; i < num_chips; i++) {
+               gc = irq_get_domain_generic_chip(domain, i * 32);
 
                gc->wake_enabled = IRQ_MSK(32);
+               gc->reg_base = intc->base + (i * CHIP_SIZE);
 
                ct = gc->chip_types;
                ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
@@ -127,21 +126,19 @@ static int __init ingenic_intc_of_init(struct device_node *node,
                ct->chip.irq_mask = irq_gc_mask_disable_reg;
                ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
                ct->chip.irq_set_wake = irq_gc_set_wake;
-               ct->chip.irq_suspend = ingenic_intc_irq_suspend;
-               ct->chip.irq_resume = ingenic_intc_irq_resume;
+               ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
 
-               irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0,
-                                      IRQ_NOPROBE | IRQ_LEVEL);
+               /* Mask all irqs */
+               irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK);
        }
 
-       domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
-                                      &irq_domain_simple_ops, NULL);
-       if (!domain)
-               pr_warn("unable to register IRQ domain\n");
-
        setup_irq(parent_irq, &intc_cascade_action);
        return 0;
 
+out_domain_remove:
+       irq_domain_remove(domain);
+out_unmap_base:
+       iounmap(intc->base);
 out_unmap_irq:
        irq_dispose_mapping(parent_irq);
 out_free: