Merge tag 'fuse-update-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/mszered...

[linux.git] / drivers / mfd / intel_soc_pmic_crc.c

diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index de3f31266c57019f833a3f92ce70d1b4f2dcd3d4..b6ab72fa056971228a2948846fcd1a42c7cec13f 100644 (file)
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -1,25 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
- * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
+ * Device access for Crystal Cove PMIC
  *
  * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version
- * 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
  * Author: Yang, Bin <bin.yang@intel.com>
  * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
  */
 
-#include <linux/mfd/core.h>
 #include <linux/interrupt.h>
 #include <linux/regmap.h>
+#include <linux/mfd/core.h>
 #include <linux/mfd/intel_soc_pmic.h>
+
 #include "intel_soc_pmic_core.h"
 
 #define CRYSTAL_COVE_MAX_REGISTER      0xC6
@@ -109,27 +102,13 @@ static const struct regmap_config crystal_cove_regmap_config = {
 };
 
 static const struct regmap_irq crystal_cove_irqs[] = {
-       [CRYSTAL_COVE_IRQ_PWRSRC] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
-       },
-       [CRYSTAL_COVE_IRQ_THRM] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_THRM),
-       },
-       [CRYSTAL_COVE_IRQ_BCU] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_BCU),
-       },
-       [CRYSTAL_COVE_IRQ_ADC] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_ADC),
-       },
-       [CRYSTAL_COVE_IRQ_CHGR] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
-       },
-       [CRYSTAL_COVE_IRQ_GPIO] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
-       },
-       [CRYSTAL_COVE_IRQ_VHDMIOCP] = {
-               .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
-       },
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
+       REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
 };
 
 static const struct regmap_irq_chip crystal_cove_irq_chip = {