drivers: Remove explicit invocations of mmiowb()

[linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index 626b491f7674fd7888ef2ba560231c999b2b1744..3716c828ff5d9537ff4bb02678b0eeb819dd2853 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -869,9 +869,6 @@ static void bnx2x_hc_int_disable(struct bnx2x *bp)
           "write %x to HC %d (addr 0x%x)\n",
           val, port, addr);
 
-       /* flush all outstanding writes */
-       mmiowb();
-
        REG_WR(bp, addr, val);
        if (REG_RD(bp, addr) != val)
                BNX2X_ERR("BUG! Proper val not read from IGU!\n");
@@ -887,9 +884,6 @@ static void bnx2x_igu_int_disable(struct bnx2x *bp)
 
        DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 
-       /* flush all outstanding writes */
-       mmiowb();
-
        REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
        if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
                BNX2X_ERR("BUG! Proper val not read from IGU!\n");
@@ -1595,7 +1589,6 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
        /*
         * Ensure that HC_CONFIG is written before leading/trailing edge config
         */
-       mmiowb();
        barrier();
 
        if (!CHIP_IS_E1(bp)) {
@@ -1611,9 +1604,6 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
                REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
                REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
        }
-
-       /* Make sure that interrupts are indeed enabled from here on */
-       mmiowb();
 }
 
 static void bnx2x_igu_int_enable(struct bnx2x *bp)
@@ -1674,9 +1664,6 @@ static void bnx2x_igu_int_enable(struct bnx2x *bp)
 
        REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
        REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
-
-       /* Make sure that interrupts are indeed enabled from here on */
-       mmiowb();
 }
 
 void bnx2x_int_enable(struct bnx2x *bp)
@@ -3833,7 +3820,6 @@ static void bnx2x_sp_prod_update(struct bnx2x *bp)
 
        REG_WR16_RELAXED(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
                         bp->spq_prod_idx);
-       mmiowb();
 }
 
 /**
@@ -5244,7 +5230,6 @@ static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
 {
        /* No memory barriers */
        storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
-       mmiowb(); /* keep prod updates ordered */
 }
 
 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
@@ -6513,7 +6498,6 @@ void bnx2x_nic_init_cnic(struct bnx2x *bp)
 
        /* flush all */
        mb();
-       mmiowb();
 }
 
 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
@@ -6553,7 +6537,6 @@ void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
 
        /* flush all before enabling interrupts */
        mb();
-       mmiowb();
 
        bnx2x_int_enable(bp);
 
@@ -7775,12 +7758,10 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
        DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
                         data, igu_addr_data);
        REG_WR(bp, igu_addr_data, data);
-       mmiowb();
        barrier();
        DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
                          ctl, igu_addr_ctl);
        REG_WR(bp, igu_addr_ctl, ctl);
-       mmiowb();
        barrier();
 
        /* wait for clean up to finish */
@@ -9550,7 +9531,6 @@ static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
 
        DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
                close ? "closing" : "opening");
-       mmiowb();
 }
 
 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
@@ -9674,7 +9654,6 @@ static void bnx2x_pxp_prep(struct bnx2x *bp)
        if (!CHIP_IS_E1(bp)) {
                REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
                REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
-               mmiowb();
        }
 }
 
@@ -9774,16 +9753,13 @@ static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
               reset_mask1 & (~not_reset_mask1));
 
        barrier();
-       mmiowb();
 
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
               reset_mask2 & (~stay_reset2));
 
        barrier();
-       mmiowb();
 
        REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
-       mmiowb();
 }
 
 /**
@@ -9867,9 +9843,6 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
        REG_WR(bp, MISC_REG_UNPREPARED, 0);
        barrier();
 
-       /* Make sure all is written to the chip before the reset */
-       mmiowb();
-
        /* Wait for 1ms to empty GLUE and PCI-E core queues,
         * PSWHST, GRC and PSWRD Tetris buffer.
         */
@@ -14828,7 +14801,6 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
                if (rc)
                        break;
 
-               mmiowb();
                barrier();
 
                /* Start accepting on iSCSI L2 ring */
@@ -14863,7 +14835,6 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
                if (!bnx2x_wait_sp_comp(bp, sp_bits))
                        BNX2X_ERR("rx_mode completion timed out!\n");
 
-               mmiowb();
                barrier();
 
                /* Unset iSCSI L2 MAC */