platform/x86: intel-ips: Use the correct style for SPDX License Identifier

[linux.git] / drivers / platform / x86 / intel_pmc_core.h

diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index 88d9c0653a5fc721cf2624f3ee472a93e8d87c35..f1a0792b3f9101cf17d9ae354d2facf5d16c28a7 100644 (file)
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Intel Core SoC Power Management Controller Header File
  *
@@ -186,6 +186,8 @@ enum ppfear_regs {
 #define ICL_NUM_IP_IGN_ALLOWED                 20
 #define ICL_PMC_LTR_WIGIG                      0x1BFC
 
+#define TGL_NUM_IP_IGN_ALLOWED                 22
+
 struct pmc_bit_map {
        const char *name;
        u32 bit_mask;
@@ -213,7 +215,7 @@ struct pmc_bit_map {
  * captures them to have a common implementation.
  */
 struct pmc_reg_map {
-       const struct pmc_bit_map *pfear_sts;
+       const struct pmc_bit_map **pfear_sts;
        const struct pmc_bit_map *mphy_sts;
        const struct pmc_bit_map *pll_sts;
        const struct pmc_bit_map **slps0_dbg_maps;
@@ -241,6 +243,9 @@ struct pmc_reg_map {
  * @pmc_xram_read_bit: flag to indicate whether PMC XRAM shadow registers
  *                     used to read MPHY PG and PLL status are available
  * @mutex_lock:                mutex to complete one transcation
+ * @check_counters:    On resume, check if counters are getting incremented
+ * @pc10_counter:      PC10 residency counter
+ * @s0ix_counter:      S0ix residency (step adjusted)
  *
  * pmc_dev contains info about power management controller device.
  */
@@ -253,6 +258,10 @@ struct pmc_dev {
 #endif /* CONFIG_DEBUG_FS */
        int pmc_xram_read_bit;
        struct mutex lock; /* generic mutex lock for PMC Core */
+
+       bool check_counters; /* Check for counter increments on resume */
+       u64 pc10_counter;
+       u64 s0ix_counter;
 };
 
 #endif /* PMC_CORE_H */