Merge branch 'pci/enumeration'

[linux.git] / include / linux / pci.h

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 73178a2fcee09b10b0e5a78a838213d9fe204b65..2619ab35dae9d448e99ebb52c91c4c9572a41c5d 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -217,6 +217,7 @@ enum pci_bus_flags {
        PCI_BUS_FLAGS_NO_MSI    = (__force pci_bus_flags_t) 1,
        PCI_BUS_FLAGS_NO_MMRBC  = (__force pci_bus_flags_t) 2,
        PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
+       PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
 };
 
 /* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
@@ -473,6 +474,7 @@ struct pci_host_bridge {
        unsigned int    native_aer:1;           /* OS may use PCIe AER */
        unsigned int    native_hotplug:1;       /* OS may use PCIe hotplug */
        unsigned int    native_pme:1;           /* OS may use PCIe PME */
+       unsigned int    native_ltr:1;           /* OS may use PCIe LTR */
        /* Resource alignment requirements */
        resource_size_t (*align_resource)(struct pci_dev *dev,
                        const struct resource *res,
@@ -1079,8 +1081,6 @@ int pcie_get_readrq(struct pci_dev *dev);
 int pcie_set_readrq(struct pci_dev *dev, int rq);
 int pcie_get_mps(struct pci_dev *dev);
 int pcie_set_mps(struct pci_dev *dev, int mps);
-int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
-                         enum pcie_link_width *width);
 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
                             enum pci_bus_speed *speed,
                             enum pcie_link_width *width);
@@ -2284,7 +2284,7 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
        return false;
 }
 
-#if defined(CONFIG_PCIEAER) || defined(CONFIG_EEH)
+#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
 void pci_uevent_ers(struct pci_dev *pdev, enum  pci_ers_result err_type);
 #endif