]> asedeno.scripts.mit.edu Git - linux.git/commit
i915/dp/fec: Cache the FEC_CAPABLE DPCD register
authorAnusha Srivatsa <anusha.srivatsa@intel.com>
Fri, 2 Nov 2018 04:14:54 +0000 (21:14 -0700)
committerManasi Navare <manasi.d.navare@intel.com>
Sat, 3 Nov 2018 01:21:21 +0000 (18:21 -0700)
commit08cadae8e1570c069f639a86fe4370485094552c
tree2243f2f5683de8e17c4033e4838828d0383839ff
parent83b466b1dc5f0b4d33f0a901e8b00197a8f3582d
i915/dp/fec: Cache the FEC_CAPABLE DPCD register

Similar to DSC DPCD registers, let us cache
FEC_CAPABLE register to avoid using stale
values. With this we can avoid aux reads
everytime and instead read the cached values.

v2: Avoid using memset and array for a single
field. (Manasi,Jani)

v3: Print FEC CAPABILITY value. (Manasi)

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181102041455.15818-1-anusha.srivatsa@intel.com
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h