]> asedeno.scripts.mit.edu Git - linux.git/commit
drm/i915/psr: Only handle interruptions of the transcoder in use
authorJosé Roberto de Souza <jose.souza@intel.com>
Wed, 4 Sep 2019 21:34:14 +0000 (14:34 -0700)
committerJosé Roberto de Souza <jose.souza@intel.com>
Thu, 5 Sep 2019 00:03:34 +0000 (17:03 -0700)
commit2f3b87124b9f08518b43abf2266035dd22fdbd3c
tree480bdf1ac53b504579e7ccf90f2df0eeae646b81
parentab016914984e2a7405756dfc8a8e4cb54a4c1b48
drm/i915/psr: Only handle interruptions of the transcoder in use

It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.

While doing this it gives us trouble on Tiger Lake if we are
reading/writing to registers of disabled transcoders since from gen12
onwards the registers are relative to the transcoder. Instead of forcing
them ON to access those registers, just avoid the accesses as they are
not needed.

v2 (Lucas):
  - Explain why we can't keep accessing all transcoders
  - Remove TODO about extending the irq handling to multiple instances:
    when/if implementing multiple instances it's pretty clear by the
    singleton psr that it needs to be extended
  - Fix intel_psr_debug_set() calling psr_irq_control() with
    psr.transcoder not set yet (from Imre). Now we only set the debug
    register right away if psr is already enabled. Otherwise we just
    record the value to be set when enabling the source.
  - Do not depend on the value of TRANSCODER_A. Just be relative to it
    (from Imre)
  - handle psr error last so we don't schedule the work before handling
    the other flags

v3:
  - Adding a warning about setting reserverd bits on EDP_PSR_IMR

Cc: Imre Deak <imre.deak@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190904213419.27547-2-jose.souza@intel.com
drivers/gpu/drm/i915/display/intel_psr.c
drivers/gpu/drm/i915/i915_reg.h