]> asedeno.scripts.mit.edu Git - linux.git/commit
drm/i915: Enable FIFO underrun reporting after initial fastset, v4.
authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Mon, 13 Nov 2017 14:40:43 +0000 (15:40 +0100)
committerMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Fri, 17 Nov 2017 11:14:25 +0000 (12:14 +0100)
commit33a49868e5d8d98f01b41f902dd487530cd56b5e
tree1b71f495ebbc3d762e816e0957f7e2299318b8fe
parent41729bf2248bc8593e5103d43974079cc269524c
drm/i915: Enable FIFO underrun reporting after initial fastset, v4.

The firmware may have set up the pipe correctly, but the FIFO
underrun and CRC interrupts are likely not enabled.

This resulted in debugfs_test.read_all_entries failing on haswell,
because of a timeout when reading the crc debugfs entry.

Solve this by enabling FIFO underrun reporting after the initial
fastset, which lets interrupts be generated as expected.

Changes since v1:
- Always enable CPU FIFO underrun reporting for >GEN2,
  and handle GEN2 correctly.
Changes since v2:
- Remove unneeded HAS_DDI, simplify GEN2 case.
Changes since v3:
- Use intel_crtc_pch_transcoder to determine pch transcoder for underruns. (Ville)
- Remove crtc->config dereference in intel_crtc_pch_transcoder. (Ville)

Testcase: debugfs_test.read_all_entries
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171113144043.58658-1-maarten.lankhorst@linux.intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
drivers/gpu/drm/i915/intel_display.c