asedeno.scripts.mit.edu Git - linux.git/commit

]> asedeno.scripts.mit.edu Git - linux.git/commit

author	Rajan Vaja <rajan.vaja@xilinx.com>
	Thu, 5 Dec 2019 06:35:54 +0000 (22:35 -0800)
committer	Stephen Boyd <sboyd@kernel.org>
	Thu, 23 Jan 2020 21:21:50 +0000 (13:21 -0800)
commit	352546805a44871b68affea09a2fbd5a48e452d0
tree	d70f29f0e6aa2c4ef1491d611eae0ad3ba91c528	tree \| snapshot
parent	e42617b825f8073569da76dc4510bfa019b1c35a	commit \| diff

dt-bindings: clock: Add bindings for versal clock driver

Add documentation to describe Xilinx Versal clock driver
bindings.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/1575527759-26452-2-git-send-email-rajan.vaja@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml	[new file with mode: 0644]	blob
include/dt-bindings/clock/xlnx-versal-clk.h	[new file with mode: 0644]	blob

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