asedeno.scripts.mit.edu Git - linux.git/commit

]> asedeno.scripts.mit.edu Git - linux.git/commit

author	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
	Mon, 19 Mar 2018 08:13:14 +0000 (17:13 +0900)
committer	Linus Walleij <linus.walleij@linaro.org>
	Tue, 27 Mar 2018 13:14:43 +0000 (15:14 +0200)
commit	4fc97ef94bbfa185d16b3e44199b7559d0668747
tree	922222a02148ea3b42cfd0e51e66c701ec670dca	tree \| snapshot
parent	c8a830904991931106c96ff1ee0588d1ca9ea5f0	commit \| diff

pinctrl: uniphier: add UART hardware flow control pin-mux settings

UniPhier SoCs have the following pins for hardware flow control of UART:
XRTS, XCTS
and for modem control of UART:
XDTR, XDSR, XDCD, XRI

The port number with the flow control is SoC-dependent.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

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drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c		diff \| blob \| history
drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c		diff \| blob \| history