]> asedeno.scripts.mit.edu Git - linux.git/commit
projects / linux.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 46a7054) | patch
mlxsw: reg: Add the Router Interface Group Version 2 register
authorYotam Gigi <yotamg@mellanox.com>
Tue, 19 Sep 2017 08:00:14 +0000 (10:00 +0200)
committerDavid S. Miller <davem@davemloft.net>
Tue, 19 Sep 2017 21:21:40 +0000 (14:21 -0700)
commit5080c7e91701744ef1a5d7aab51f568f889bfddb
tree837427d4273ec50d7f3b26a4fa0388475dcac6bftree | snapshot
parent46a7054ebace0fcd0d1826881aa5ab219faa6a77commit | diff
mlxsw: reg: Add the Router Interface Group Version 2 register

The RIGR-V2 register is used to add, remove and query egress interface list
of a multicast forwarding entry and it will be used by the multicast
router offloading logic.

Signed-off-by: Yotam Gigi <yotamg@mellanox.com>
Reviewed-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlxsw/reg.h diff | blob | history
local clone of linux.git