]> asedeno.scripts.mit.edu Git - linux.git/commit
ARM: dts: NSP: Fix PPI interrupt types
authorFlorian Fainelli <f.fainelli@gmail.com>
Tue, 7 Nov 2017 19:10:29 +0000 (11:10 -0800)
committerFlorian Fainelli <f.fainelli@gmail.com>
Mon, 27 Nov 2017 19:22:29 +0000 (11:22 -0800)
commit5f1aa51c7a1eef1c5a60b8334e32c89904964245
treebc7d4e3c07dc4e31a07d9cd1283c110f39602e40
parent77416ab35f5712382e5a792bfa1736ceb70d5bbb
ARM: dts: NSP: Fix PPI interrupt types

Booting a kernel results in the kernel warning us about the following
PPI interrupts configuration:
[    0.105127] smp: Bringing up secondary CPUs ...
[    0.110545] GIC: PPI11 is secure or misconfigured
[    0.110551] GIC: PPI13 is secure or misconfigured

Fix this by using the appropriate edge configuration for PPI11 and
PPI13, this is similar to what was fixed for Northstar (BCM5301X) in
commit 0e34079cd1f6 ("ARM: dts: BCM5301X: Correct GIC_PPI interrupt
flags").

Fixes: 7b2e987de207 ("ARM: NSP: add minimal Northstar Plus device tree")
Fixes: 1a9d53cabaf4 ("ARM: dts: NSP: Add TWD Support to DT")
Acked-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
arch/arm/boot/dts/bcm-nsp.dtsi