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clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig
authorMylène Josserand <mylene.josserand@free-electrons.com>
Tue, 17 Jan 2017 14:02:22 +0000 (15:02 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Tue, 17 Jan 2017 16:42:46 +0000 (17:42 +0100)
commit603a0c8af9cb23f7cf94d57e76113fef51848200
tree0fb26415f874bacf728d62db4c55209ff6c3d254tree | snapshot
parent70421257c068b91476e70cade15fca68045d0693commit | diff
clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig

The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.

Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-a33.c diff | blob | history
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