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media: Fix Lane mapping in Cadence CSI2TX
authorJan Kotas <jank@cadence.com>
Mon, 22 Jul 2019 08:22:22 +0000 (04:22 -0400)
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Thu, 25 Jul 2019 10:43:01 +0000 (06:43 -0400)
commit6ded416d4ac4ecbf104b897661cdfa2cdacf022a
tree963e756610e111613fb267be99ba0f7e1fdc68bdtree | snapshot
parentbf9df90b3557ec6d5d92914da6a61453741d3e13commit | diff
media: Fix Lane mapping in Cadence CSI2TX

This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.

Signed-off-by: Jan Kotas <jank@cadence.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
drivers/media/platform/cadence/cdns-csi2tx.c diff | blob | history
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