asedeno.scripts.mit.edu Git - linux.git/commit

]> asedeno.scripts.mit.edu Git - linux.git/commit

author	Masahiro Yamada <yamada.masahiro@socionext.com>
	Fri, 2 Oct 2015 04:42:21 +0000 (13:42 +0900)
committer	Olof Johansson <olof@lixom.net>
	Tue, 27 Oct 2015 00:21:02 +0000 (09:21 +0900)
commit	7c62f299bafef82c83169ac0c4cf77874446fc83
tree	ff7f1ce4d392a456c0394e9946ae1befca0aaf8f	tree \| snapshot
parent	3d2ef3b3962c60e3b25de6a981127d95cb0be98b	commit \| diff

ARM: dts: uniphier: add outer cache controller nodes

Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

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arch/arm/boot/dts/uniphier-ph1-ld4.dtsi		diff \| blob \| history
arch/arm/boot/dts/uniphier-ph1-pro4.dtsi		diff \| blob \| history
arch/arm/boot/dts/uniphier-ph1-pro5.dtsi		diff \| blob \| history
arch/arm/boot/dts/uniphier-ph1-sld3.dtsi		diff \| blob \| history
arch/arm/boot/dts/uniphier-ph1-sld8.dtsi		diff \| blob \| history
arch/arm/boot/dts/uniphier-proxstream2.dtsi		diff \| blob \| history