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clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled
authorSekhar Nori <nsekhar@ti.com>
Fri, 25 May 2018 18:11:45 +0000 (13:11 -0500)
committerMichael Turquette <mturquette@baylibre.com>
Wed, 30 May 2018 19:48:27 +0000 (12:48 -0700)
commit7f02f18e7f87831747aaa2685f63d16fb2649c6a
treeadac6daea157c91d4db8fe86c582ebd4a9e26900tree | snapshot
parent715478bb63ffd76cf90f6536be8592e3f6df9567commit | diff
clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com
drivers/clk/davinci/pll-dm646x.c diff | blob | history
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