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ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+
authorDmitry Osipenko <digetx@gmail.com>
Sat, 24 Nov 2018 21:13:46 +0000 (00:13 +0300)
committerThierry Reding <treding@nvidia.com>
Wed, 16 Jan 2019 12:21:45 +0000 (13:21 +0100)
commit82cdfc382b940b441e93188507c5ae68f9582e3d
tree387ca6b3cbb2323132a75857664d27c0172233b7tree | snapshot
parentbfeffd155283772bbe78c6a05dec7c0128ee500ccommit | diff
ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
arch/arm/mach-tegra/sleep-tegra30.S diff | blob | history
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