]> asedeno.scripts.mit.edu Git - linux.git/commit
Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind...
authorStephen Boyd <sboyd@kernel.org>
Tue, 5 Feb 2019 22:07:52 +0000 (14:07 -0800)
committerStephen Boyd <sboyd@kernel.org>
Tue, 5 Feb 2019 22:07:52 +0000 (14:07 -0800)
commita49ba41c53d1da529e0573e08d5991abb72eaedf
treebe8f06d8817086217a331a4a356b1b753f1bd23b
parentbfeffd155283772bbe78c6a05dec7c0128ee500c
parent491b00ff699356a8dab10eb517a1b44205514c9e
Merge tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip

Pull Rockchip clk driver updates from Heiko Stuebner:

Fix for PLL rate calculation on rk3328 and SET_RATE_PARENT flag
for the display clock on rk3066.

* tag 'v5.1-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328