]> asedeno.scripts.mit.edu Git - linux.git/commit
clk: sunxi-ng: sun5i: Fix mux width for csi clock
authorPriit Laes <plaes@plaes.org>
Thu, 2 Mar 2017 20:55:27 +0000 (22:55 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Mon, 6 Mar 2017 09:25:56 +0000 (10:25 +0100)
commitb0f0daa8fe9e74b85f6360288d38224ad1c2f2f4
tree1f0b619bb03802fdfd07dd854b3c11f6973e5b81
parent05c04bef445d695917fe74422e05352b1b46f3c8
clk: sunxi-ng: sun5i: Fix mux width for csi clock

Mux for CSI clock is 3 bits, not 2.

Signed-off-by: Priit Laes <plaes@plaes.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun5i.c