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drm/i915/icl: compute the combo PHY (DPLL) DP registers
authorPaulo Zanoni <paulo.r.zanoni@intel.com>
Wed, 28 Mar 2018 21:58:00 +0000 (14:58 -0700)
committerPaulo Zanoni <paulo.r.zanoni@intel.com>
Mon, 7 May 2018 23:44:54 +0000 (16:44 -0700)
commitbb82139b4bbf8bdb825a7339d34d231632e67f27
tree35c637b0ab13ae46c746b550c159955c5bd6aee1tree | snapshot
parentfebafb93181e4fb4de19f4484df62ce2d04155aacommit | diff
drm/i915/icl: compute the combo PHY (DPLL) DP registers

Just use the hardcoded tables provided by our spec.

v2: Rebase.
v3: Clarify that 38.4 uses the 19.2 table (James).

Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328215803.13835-6-paulo.r.zanoni@intel.com
drivers/gpu/drm/i915/intel_dpll_mgr.c diff | blob | history
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