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ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
authorDaniel Schultz <d.schultz@phytec.de>
Mon, 5 Mar 2018 12:45:11 +0000 (13:45 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 16 Apr 2018 12:13:04 +0000 (14:13 +0200)
commitc887f5b0210c5c7d30e2da47c37798eb6f37f563
tree6a46ca2cf7980f49387ca334b6dce30f5b6d4409tree | snapshot
parent5f501b42f35678615bef3f00dfb277eff1c58dfbcommit | diff
ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som

The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm/boot/dts/rk3288-phycore-som.dtsi diff | blob | history
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