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(parent: 5c59801) | patch
clk: sunxi: A31: Fix wrong AHB gate number
authorAndre Przywara <andre.przywara@arm.com>
Wed, 23 Jan 2019 00:59:11 +0000 (00:59 +0000)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 28 Jan 2019 08:26:32 +0000 (09:26 +0100)
commitee0b27a3a4da0b0ed2318aa092f8856896e9450b
tree37dac0f2b5e3a838c099b1efe1d02f75e986f6bbtree | snapshot
parent5c59801f7018acba11b12de59017a3fcdcf7421dcommit | diff
clk: sunxi: A31: Fix wrong AHB gate number

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c diff | blob | history
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