]> asedeno.scripts.mit.edu Git - linux.git/commit
tty: serial: fsl_lpuart: correct the FIFO depth size
authorFugang Duan <fugang.duan@nxp.com>
Wed, 17 Jul 2019 05:19:30 +0000 (13:19 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 4 Sep 2019 10:43:45 +0000 (12:43 +0200)
commitf77ebb241ce00ec99ed4e42ff3ab38dd6d1ce6f5
tree21c9df095ee8db1e58aae077ffbea8ce7467e1f4
parent638341d5dbd11f057a9b00176ade767b08a9e95f
tty: serial: fsl_lpuart: correct the FIFO depth size

VF610/LS1021a/i.MX7ULP/i.MX8QXP reference manual describe the
TXFIFOSIZE/RXFIFOSIZE field as below.

000b - FIFO/Buffer depth = 1 dataword.
001b - FIFO/Buffer depth = 4 datawords.
010b - FIFO/Buffer depth = 8 datawords.
011b - FIFO/Buffer depth = 16 datawords.
100b - FIFO/Buffer depth = 32 datawords.
101b - FIFO/Buffer depth = 64 datawords.
110b - FIFO/Buffer depth = 128 datawords.
111b - FIFO/Buffer depth = 256 datawords. (Reserved for VF610)

So the FIFO depth should be: 0x1 << (val ? (val + 1) : 0)

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Link: https://lore.kernel.org/r/20190717051930.15514-6-fugang.duan@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/fsl_lpuart.c